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Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is accessible via the system registers. The TRBE supports different addressing modes including CPU virtual address and buffer modes including the circular buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1), an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the access to the trace buffer could be prohibited by a higher exception level (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU private interrupt (PPI) on address translation errors and when the buffer is full. Overall implementation here is inspired from the Arm SPE driver. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> [ Mark the buffer truncated on WRAP event, error code cleanup ] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-18-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> |
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| .. | ||
| coresight-catu.c | ||
| coresight-catu.h | ||
| coresight-core.c | ||
| coresight-cpu-debug.c | ||
| coresight-cti-core.c | ||
| coresight-cti-platform.c | ||
| coresight-cti-sysfs.c | ||
| coresight-cti.h | ||
| coresight-etb10.c | ||
| coresight-etm-cp14.c | ||
| coresight-etm-perf.c | ||
| coresight-etm-perf.h | ||
| coresight-etm.h | ||
| coresight-etm3x-core.c | ||
| coresight-etm3x-sysfs.c | ||
| coresight-etm4x-core.c | ||
| coresight-etm4x-sysfs.c | ||
| coresight-etm4x.h | ||
| coresight-funnel.c | ||
| coresight-platform.c | ||
| coresight-priv.h | ||
| coresight-replicator.c | ||
| coresight-stm.c | ||
| coresight-sysfs.c | ||
| coresight-tmc-core.c | ||
| coresight-tmc-etf.c | ||
| coresight-tmc-etr.c | ||
| coresight-tmc.h | ||
| coresight-tpiu.c | ||
| coresight-trbe.c | ||
| coresight-trbe.h | ||
| Kconfig | ||
| Makefile | ||