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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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df762eccba
Conflicts: arch/arm/include/asm/atomic.h arch/arm/include/asm/hardirq.h arch/arm/kernel/smp.c
474 lines
9.7 KiB
C
474 lines
9.7 KiB
C
/*
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* arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_ATOMIC_H
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#define __ASM_ARM_ATOMIC_H
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#include <linux/compiler.h>
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#include <linux/prefetch.h>
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#include <linux/types.h>
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#include <linux/irqflags.h>
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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#define ATOMIC_INIT(i) { (i) }
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#ifdef __KERNEL__
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/*
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* On ARM, ordinary assignment (str instruction) doesn't clear the local
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* strex/ldrex monitor on some implementations. The reason we can use it for
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* atomic_set() is the clrex or dummy strex done on every exception return.
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*/
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#define atomic_read(v) (*(volatile int *)&(v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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#if __LINUX_ARM_ARCH__ >= 6
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/*
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* ARMv6 UP and SMP safe atomic ops. We use load exclusive and
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* store exclusive to ensure that these are atomic. We may loop
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* to ensure that the update happens.
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*/
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static inline void atomic_add(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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prefetchw(&v->counter);
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__asm__ __volatile__("@ atomic_add\n"
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"1: ldrex %0, [%3]\n"
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" add %0, %0, %4\n"
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" strex %1, %0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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smp_mb();
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__asm__ __volatile__("@ atomic_add_return\n"
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"1: ldrex %0, [%3]\n"
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" add %0, %0, %4\n"
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" strex %1, %0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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smp_mb();
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return result;
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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prefetchw(&v->counter);
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__asm__ __volatile__("@ atomic_sub\n"
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"1: ldrex %0, [%3]\n"
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" sub %0, %0, %4\n"
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" strex %1, %0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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smp_mb();
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__asm__ __volatile__("@ atomic_sub_return\n"
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"1: ldrex %0, [%3]\n"
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" sub %0, %0, %4\n"
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" strex %1, %0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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smp_mb();
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return result;
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}
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static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
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{
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int oldval;
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unsigned long res;
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smp_mb();
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do {
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__asm__ __volatile__("@ atomic_cmpxchg\n"
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"ldrex %1, [%3]\n"
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"mov %0, #0\n"
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"teq %1, %4\n"
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"strexeq %0, %5, [%3]\n"
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: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
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: "r" (&ptr->counter), "Ir" (old), "r" (new)
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: "cc");
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} while (res);
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smp_mb();
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return oldval;
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}
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#else /* ARM_ARCH_6 */
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#ifdef CONFIG_SMP
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#error SMP not supported on pre-ARMv6 CPUs
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#endif
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long flags;
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int val;
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raw_local_irq_save(flags);
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val = v->counter;
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v->counter = val += i;
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raw_local_irq_restore(flags);
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return val;
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}
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#define atomic_add(i, v) (void) atomic_add_return(i, v)
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long flags;
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int val;
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raw_local_irq_save(flags);
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val = v->counter;
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v->counter = val -= i;
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raw_local_irq_restore(flags);
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return val;
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}
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#define atomic_sub(i, v) (void) atomic_sub_return(i, v)
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static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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int ret;
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unsigned long flags;
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raw_local_irq_save(flags);
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ret = v->counter;
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if (likely(ret == old))
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v->counter = new;
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raw_local_irq_restore(flags);
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return ret;
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}
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#endif /* __LINUX_ARM_ARCH__ */
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int c, old;
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c = atomic_read(v);
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while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
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c = old;
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return c;
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}
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#define atomic_inc(v) atomic_add(1, v)
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#define atomic_dec(v) atomic_sub(1, v)
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#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
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#define atomic_inc_return(v) (atomic_add_return(1, v))
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#define atomic_dec_return(v) (atomic_sub_return(1, v))
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#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
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#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#ifndef CONFIG_GENERIC_ATOMIC64
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typedef struct {
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long long counter;
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} atomic64_t;
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#define ATOMIC64_INIT(i) { (i) }
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#ifdef CONFIG_ARM_LPAE
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static inline long long atomic64_read(const atomic64_t *v)
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{
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long long result;
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__asm__ __volatile__("@ atomic64_read\n"
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" ldrd %0, %H0, [%1]"
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: "=&r" (result)
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: "r" (&v->counter), "Qo" (v->counter)
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);
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return result;
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}
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static inline void atomic64_set(atomic64_t *v, long long i)
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{
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__asm__ __volatile__("@ atomic64_set\n"
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" strd %2, %H2, [%1]"
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: "=Qo" (v->counter)
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: "r" (&v->counter), "r" (i)
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);
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}
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#else
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static inline long long atomic64_read(const atomic64_t *v)
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{
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long long result;
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__asm__ __volatile__("@ atomic64_read\n"
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" ldrexd %0, %H0, [%1]"
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: "=&r" (result)
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: "r" (&v->counter), "Qo" (v->counter)
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);
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return result;
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}
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static inline void atomic64_set(atomic64_t *v, long long i)
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{
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long long tmp;
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prefetchw(&v->counter);
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__asm__ __volatile__("@ atomic64_set\n"
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"1: ldrexd %0, %H0, [%2]\n"
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" strexd %0, %3, %H3, [%2]\n"
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" teq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp), "=Qo" (v->counter)
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: "r" (&v->counter), "r" (i)
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: "cc");
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}
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#endif
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static inline void atomic64_add(long long i, atomic64_t *v)
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{
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long long result;
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unsigned long tmp;
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prefetchw(&v->counter);
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__asm__ __volatile__("@ atomic64_add\n"
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"1: ldrexd %0, %H0, [%3]\n"
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" adds %Q0, %Q0, %Q4\n"
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" adc %R0, %R0, %R4\n"
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" strexd %1, %0, %H0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "r" (i)
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: "cc");
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}
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static inline long long atomic64_add_return(long long i, atomic64_t *v)
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{
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long long result;
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unsigned long tmp;
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smp_mb();
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__asm__ __volatile__("@ atomic64_add_return\n"
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"1: ldrexd %0, %H0, [%3]\n"
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" adds %Q0, %Q0, %Q4\n"
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" adc %R0, %R0, %R4\n"
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" strexd %1, %0, %H0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "r" (i)
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: "cc");
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smp_mb();
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return result;
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}
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static inline void atomic64_sub(long long i, atomic64_t *v)
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{
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long long result;
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unsigned long tmp;
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prefetchw(&v->counter);
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__asm__ __volatile__("@ atomic64_sub\n"
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"1: ldrexd %0, %H0, [%3]\n"
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" subs %Q0, %Q0, %Q4\n"
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" sbc %R0, %R0, %R4\n"
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" strexd %1, %0, %H0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "r" (i)
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: "cc");
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}
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static inline long long atomic64_sub_return(long long i, atomic64_t *v)
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{
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long long result;
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unsigned long tmp;
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smp_mb();
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__asm__ __volatile__("@ atomic64_sub_return\n"
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"1: ldrexd %0, %H0, [%3]\n"
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" subs %Q0, %Q0, %Q4\n"
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" sbc %R0, %R0, %R4\n"
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" strexd %1, %0, %H0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "r" (i)
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: "cc");
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smp_mb();
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return result;
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}
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static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old,
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long long new)
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{
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long long oldval;
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unsigned long res;
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smp_mb();
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do {
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__asm__ __volatile__("@ atomic64_cmpxchg\n"
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"ldrexd %1, %H1, [%3]\n"
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"mov %0, #0\n"
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"teq %1, %4\n"
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"teqeq %H1, %H4\n"
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"strexdeq %0, %5, %H5, [%3]"
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: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
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: "r" (&ptr->counter), "r" (old), "r" (new)
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: "cc");
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} while (res);
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smp_mb();
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return oldval;
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}
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static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
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{
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long long result;
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unsigned long tmp;
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smp_mb();
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__asm__ __volatile__("@ atomic64_xchg\n"
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"1: ldrexd %0, %H0, [%3]\n"
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" strexd %1, %4, %H4, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
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: "r" (&ptr->counter), "r" (new)
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: "cc");
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smp_mb();
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return result;
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}
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static inline long long atomic64_dec_if_positive(atomic64_t *v)
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{
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long long result;
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unsigned long tmp;
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smp_mb();
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__asm__ __volatile__("@ atomic64_dec_if_positive\n"
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"1: ldrexd %0, %H0, [%3]\n"
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" subs %Q0, %Q0, #1\n"
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" sbc %R0, %R0, #0\n"
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" teq %R0, #0\n"
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" bmi 2f\n"
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" strexd %1, %0, %H0, [%3]\n"
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" teq %1, #0\n"
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" bne 1b\n"
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"2:"
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter)
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: "cc");
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smp_mb();
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return result;
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}
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static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
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{
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long long val;
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unsigned long tmp;
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int ret = 1;
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smp_mb();
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__asm__ __volatile__("@ atomic64_add_unless\n"
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"1: ldrexd %0, %H0, [%4]\n"
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" teq %0, %5\n"
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" teqeq %H0, %H5\n"
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" moveq %1, #0\n"
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" beq 2f\n"
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" adds %Q0, %Q0, %Q6\n"
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" adc %R0, %R0, %R6\n"
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" strexd %2, %0, %H0, [%4]\n"
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" teq %2, #0\n"
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" bne 1b\n"
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"2:"
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: "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "r" (u), "r" (a)
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: "cc");
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if (ret)
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smp_mb();
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return ret;
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}
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#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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#define atomic64_inc(v) atomic64_add(1LL, (v))
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#define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
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#define atomic64_dec(v) atomic64_sub(1LL, (v))
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#define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
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#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
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#endif /* !CONFIG_GENERIC_ATOMIC64 */
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#endif
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#endif
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