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![Robin Murphy](/assets/img/avatar_default.png)
Once we remove the serialising spinlock, a potential race opens up for non-coherent IOMMUs whereby a caller of .map() can be sure that cache maintenance has been performed on their new PTE, but will have no guarantee that such maintenance for table entries above it has actually completed (e.g. if another CPU took an interrupt immediately after writing the table entry, but before initiating the DMA sync). Handling this race safely will add some potentially non-trivial overhead to installing a table entry, which we would much rather avoid on coherent systems where it will be unnecessary, and where we are stirivng to minimise latency by removing the locking in the first place. To that end, let's introduce an explicit notion of cache-coherency to io-pgtable, such that we will be able to avoid penalising IOMMUs which know enough to know when they are coherent. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
214 lines
6.9 KiB
C
214 lines
6.9 KiB
C
#ifndef __IO_PGTABLE_H
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#define __IO_PGTABLE_H
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#include <linux/bitops.h>
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/*
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* Public API for use by IOMMU drivers
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*/
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enum io_pgtable_fmt {
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ARM_32_LPAE_S1,
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ARM_32_LPAE_S2,
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ARM_64_LPAE_S1,
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ARM_64_LPAE_S2,
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ARM_V7S,
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IO_PGTABLE_NUM_FMTS,
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};
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/**
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* struct iommu_gather_ops - IOMMU callbacks for TLB and page table management.
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*
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* @tlb_flush_all: Synchronously invalidate the entire TLB context.
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* @tlb_add_flush: Queue up a TLB invalidation for a virtual address range.
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* @tlb_sync: Ensure any queued TLB invalidation has taken effect, and
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* any corresponding page table updates are visible to the
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* IOMMU.
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*
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* Note that these can all be called in atomic context and must therefore
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* not block.
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*/
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struct iommu_gather_ops {
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void (*tlb_flush_all)(void *cookie);
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void (*tlb_add_flush)(unsigned long iova, size_t size, size_t granule,
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bool leaf, void *cookie);
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void (*tlb_sync)(void *cookie);
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};
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/**
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* struct io_pgtable_cfg - Configuration data for a set of page tables.
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*
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* @quirks: A bitmap of hardware quirks that require some special
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* action by the low-level page table allocator.
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* @pgsize_bitmap: A bitmap of page sizes supported by this set of page
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* tables.
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* @ias: Input address (iova) size, in bits.
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* @oas: Output address (paddr) size, in bits.
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* @tlb: TLB management callbacks for this set of tables.
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* @iommu_dev: The device representing the DMA configuration for the
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* page table walker.
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*/
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struct io_pgtable_cfg {
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/*
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* IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits in
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* stage 1 PTEs, for hardware which insists on validating them
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* even in non-secure state where they should normally be ignored.
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*
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* IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE and
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* IOMMU_NOEXEC flags and map everything with full access, for
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* hardware which does not implement the permissions of a given
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* format, and/or requires some format-specific default value.
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*
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* IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching invalid
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* (unmapped) entries but the hardware might do so anyway, perform
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* TLB maintenance when mapping as well as when unmapping.
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*
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* IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
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* PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
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* when the SoC is in "4GB mode" and they can only access the high
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* remap of DRAM (0x1_00000000 to 0x1_ffffffff).
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*
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* IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
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* be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
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* software-emulated IOMMU), such that pagetable updates need not
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* be treated as explicit DMA data.
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*/
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#define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
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#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
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#define IO_PGTABLE_QUIRK_TLBI_ON_MAP BIT(2)
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#define IO_PGTABLE_QUIRK_ARM_MTK_4GB BIT(3)
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#define IO_PGTABLE_QUIRK_NO_DMA BIT(4)
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unsigned long quirks;
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unsigned long pgsize_bitmap;
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unsigned int ias;
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unsigned int oas;
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const struct iommu_gather_ops *tlb;
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struct device *iommu_dev;
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/* Low-level data specific to the table format */
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union {
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struct {
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u64 ttbr[2];
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u64 tcr;
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u64 mair[2];
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} arm_lpae_s1_cfg;
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struct {
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u64 vttbr;
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u64 vtcr;
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} arm_lpae_s2_cfg;
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struct {
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u32 ttbr[2];
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u32 tcr;
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u32 nmrr;
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u32 prrr;
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} arm_v7s_cfg;
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};
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};
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/**
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* struct io_pgtable_ops - Page table manipulation API for IOMMU drivers.
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*
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* @map: Map a physically contiguous memory region.
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* @unmap: Unmap a physically contiguous memory region.
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* @iova_to_phys: Translate iova to physical address.
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*
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* These functions map directly onto the iommu_ops member functions with
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* the same names.
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*/
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struct io_pgtable_ops {
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int (*map)(struct io_pgtable_ops *ops, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot);
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int (*unmap)(struct io_pgtable_ops *ops, unsigned long iova,
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size_t size);
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phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops,
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unsigned long iova);
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};
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/**
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* alloc_io_pgtable_ops() - Allocate a page table allocator for use by an IOMMU.
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*
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* @fmt: The page table format.
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* @cfg: The page table configuration. This will be modified to represent
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* the configuration actually provided by the allocator (e.g. the
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* pgsize_bitmap may be restricted).
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* @cookie: An opaque token provided by the IOMMU driver and passed back to
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* the callback routines in cfg->tlb.
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*/
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struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,
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struct io_pgtable_cfg *cfg,
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void *cookie);
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/**
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* free_io_pgtable_ops() - Free an io_pgtable_ops structure. The caller
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* *must* ensure that the page table is no longer
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* live, but the TLB can be dirty.
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*
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* @ops: The ops returned from alloc_io_pgtable_ops.
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*/
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void free_io_pgtable_ops(struct io_pgtable_ops *ops);
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/*
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* Internal structures for page table allocator implementations.
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*/
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/**
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* struct io_pgtable - Internal structure describing a set of page tables.
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*
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* @fmt: The page table format.
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* @cookie: An opaque token provided by the IOMMU driver and passed back to
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* any callback routines.
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* @tlb_sync_pending: Private flag for optimising out redundant syncs.
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* @cfg: A copy of the page table configuration.
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* @ops: The page table operations in use for this set of page tables.
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*/
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struct io_pgtable {
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enum io_pgtable_fmt fmt;
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void *cookie;
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bool tlb_sync_pending;
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struct io_pgtable_cfg cfg;
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struct io_pgtable_ops ops;
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};
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#define io_pgtable_ops_to_pgtable(x) container_of((x), struct io_pgtable, ops)
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static inline void io_pgtable_tlb_flush_all(struct io_pgtable *iop)
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{
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iop->cfg.tlb->tlb_flush_all(iop->cookie);
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iop->tlb_sync_pending = true;
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}
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static inline void io_pgtable_tlb_add_flush(struct io_pgtable *iop,
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unsigned long iova, size_t size, size_t granule, bool leaf)
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{
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iop->cfg.tlb->tlb_add_flush(iova, size, granule, leaf, iop->cookie);
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iop->tlb_sync_pending = true;
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}
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static inline void io_pgtable_tlb_sync(struct io_pgtable *iop)
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{
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if (iop->tlb_sync_pending) {
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iop->cfg.tlb->tlb_sync(iop->cookie);
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iop->tlb_sync_pending = false;
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}
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}
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/**
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* struct io_pgtable_init_fns - Alloc/free a set of page tables for a
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* particular format.
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*
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* @alloc: Allocate a set of page tables described by cfg.
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* @free: Free the page tables associated with iop.
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*/
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struct io_pgtable_init_fns {
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struct io_pgtable *(*alloc)(struct io_pgtable_cfg *cfg, void *cookie);
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void (*free)(struct io_pgtable *iop);
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};
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extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns;
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#endif /* __IO_PGTABLE_H */
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