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![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
355 lines
9.2 KiB
C
355 lines
9.2 KiB
C
/*
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* Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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* Development of this chipset driver was funded
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* by the nice folks at National Semiconductor.
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*
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* Documentation:
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* Available from National Semiconductor
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <linux/pm.h>
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#include <asm/io.h>
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#define DRV_NAME "sc1200"
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#define SC1200_REV_A 0x00
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#define SC1200_REV_B1 0x01
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#define SC1200_REV_B3 0x02
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#define SC1200_REV_C1 0x03
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#define SC1200_REV_D1 0x04
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#define PCI_CLK_33 0x00
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#define PCI_CLK_48 0x01
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#define PCI_CLK_66 0x02
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#define PCI_CLK_33A 0x03
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static unsigned short sc1200_get_pci_clock (void)
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{
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unsigned char chip_id, silicon_revision;
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unsigned int pci_clock;
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/*
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* Check the silicon revision, as not all versions of the chip
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* have the register with the fast PCI bus timings.
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*/
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chip_id = inb (0x903c);
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silicon_revision = inb (0x903d);
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// Read the fast pci clock frequency
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if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
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pci_clock = PCI_CLK_33;
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} else {
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// check clock generator configuration (cfcc)
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// the clock is in bits 8 and 9 of this word
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pci_clock = inw (0x901e);
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pci_clock >>= 8;
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pci_clock &= 0x03;
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if (pci_clock == PCI_CLK_33A)
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pci_clock = PCI_CLK_33;
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}
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return pci_clock;
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}
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/*
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* Here are the standard PIO mode 0-4 timings for each "format".
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* Format-0 uses fast data reg timings, with slower command reg timings.
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* Format-1 uses fast timings for all registers, but won't work with all drives.
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*/
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static const unsigned int sc1200_pio_timings[4][5] =
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{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
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{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
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{0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
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{0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
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/*
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* After chip reset, the PIO timings are set to 0x00009172, which is not valid.
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*/
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//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
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static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *pdev = to_pci_dev(hwif->dev);
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unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
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pci_read_config_dword(pdev, basereg + 4, &format);
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format = (format >> 31) & 1;
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if (format)
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format += sc1200_get_pci_clock();
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pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
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sc1200_pio_timings[format][pio]);
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}
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/*
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* The SC1200 specifies that two drives sharing a cable cannot mix
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* UDMA/MDMA. It has to be one or the other, for the pair, though
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* different timings can still be chosen for each drive. We could
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* set the appropriate timing bits on the fly, but that might be
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* a bit confusing. So, for now we statically handle this requirement
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* by looking at our mate drive to see what it is capable of, before
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* choosing a mode for our own drive.
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*/
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static u8 sc1200_udma_filter(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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ide_drive_t *mate = ide_get_pair_dev(drive);
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u16 *mateid;
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u8 mask = hwif->ultra_mask;
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if (mate == NULL)
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goto out;
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mateid = mate->id;
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if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
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if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
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(mateid[ATA_ID_UDMA_MODES] & 7))
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goto out;
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if (mateid[ATA_ID_MWDMA_MODES] & 7)
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mask = 0;
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}
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out:
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return mask;
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}
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static void sc1200_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned int reg, timings;
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unsigned short pci_clock;
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unsigned int basereg = hwif->channel ? 0x50 : 0x40;
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const u8 mode = drive->dma_mode;
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static const u32 udma_timing[3][3] = {
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{ 0x00921250, 0x00911140, 0x00911030 },
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{ 0x00932470, 0x00922260, 0x00922140 },
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{ 0x009436a1, 0x00933481, 0x00923261 },
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};
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static const u32 mwdma_timing[3][3] = {
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{ 0x00077771, 0x00012121, 0x00002020 },
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{ 0x000bbbb2, 0x00024241, 0x00013131 },
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{ 0x000ffff3, 0x00035352, 0x00015151 },
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};
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pci_clock = sc1200_get_pci_clock();
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/*
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* Note that each DMA mode has several timings associated with it.
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* The correct timing depends on the fast PCI clock freq.
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*/
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if (mode >= XFER_UDMA_0)
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timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
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else
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timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
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if ((drive->dn & 1) == 0) {
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pci_read_config_dword(dev, basereg + 4, ®);
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timings |= reg & 0x80000000; /* preserve PIO format bit */
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pci_write_config_dword(dev, basereg + 4, timings);
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} else
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pci_write_config_dword(dev, basereg + 12, timings);
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}
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/* Replacement for the standard ide_dma_end action in
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* dma_proc.
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*
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* returns 1 on error, 0 otherwise
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*/
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static int sc1200_dma_end(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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unsigned long dma_base = hwif->dma_base;
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u8 dma_stat;
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dma_stat = inb(dma_base+2); /* get DMA status */
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if (!(dma_stat & 4))
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printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
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dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
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outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
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outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
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return (dma_stat & 7) != 4; /* verify good DMA status */
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}
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/*
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* sc1200_set_pio_mode() handles setting of PIO modes
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* for both the chipset and drive.
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*
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* All existing BIOSs for this chipset guarantee that all drives
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* will have valid default PIO timings set up before we get here.
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*/
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static void sc1200_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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int mode = -1;
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const u8 pio = drive->pio_mode - XFER_PIO_0;
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/*
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* bad abuse of ->set_pio_mode interface
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*/
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switch (pio) {
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case 200: mode = XFER_UDMA_0; break;
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case 201: mode = XFER_UDMA_1; break;
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case 202: mode = XFER_UDMA_2; break;
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case 100: mode = XFER_MW_DMA_0; break;
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case 101: mode = XFER_MW_DMA_1; break;
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case 102: mode = XFER_MW_DMA_2; break;
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}
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if (mode != -1) {
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printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
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ide_dma_off_quietly(drive);
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if (ide_set_dma_mode(drive, mode) == 0 &&
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(drive->dev_flags & IDE_DFLAG_USING_DMA))
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hwif->dma_ops->dma_host_set(drive, 1);
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return;
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}
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sc1200_tunepio(drive, pio);
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}
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#ifdef CONFIG_PM
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struct sc1200_saved_state {
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u32 regs[8];
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};
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static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
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{
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printk("SC1200: suspend(%u)\n", state.event);
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/*
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* we only save state when going from full power to less
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*/
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if (state.event == PM_EVENT_ON) {
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struct ide_host *host = pci_get_drvdata(dev);
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struct sc1200_saved_state *ss = host->host_priv;
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unsigned int r;
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/*
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* save timing registers
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* (this may be unnecessary if BIOS also does it)
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*/
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for (r = 0; r < 8; r++)
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pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
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}
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pci_disable_device(dev);
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pci_set_power_state(dev, pci_choose_state(dev, state));
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return 0;
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}
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static int sc1200_resume (struct pci_dev *dev)
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{
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struct ide_host *host = pci_get_drvdata(dev);
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struct sc1200_saved_state *ss = host->host_priv;
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unsigned int r;
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int i;
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i = pci_enable_device(dev);
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if (i)
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return i;
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/*
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* restore timing registers
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* (this may be unnecessary if BIOS also does it)
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*/
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for (r = 0; r < 8; r++)
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pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
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return 0;
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}
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#endif
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static const struct ide_port_ops sc1200_port_ops = {
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.set_pio_mode = sc1200_set_pio_mode,
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.set_dma_mode = sc1200_set_dma_mode,
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.udma_filter = sc1200_udma_filter,
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};
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static const struct ide_dma_ops sc1200_dma_ops = {
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.dma_host_set = ide_dma_host_set,
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.dma_setup = ide_dma_setup,
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.dma_start = ide_dma_start,
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.dma_end = sc1200_dma_end,
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.dma_test_irq = ide_dma_test_irq,
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.dma_lost_irq = ide_dma_lost_irq,
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.dma_timer_expiry = ide_dma_sff_timer_expiry,
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.dma_sff_read_status = ide_dma_sff_read_status,
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};
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static const struct ide_port_info sc1200_chipset __devinitdata = {
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.name = DRV_NAME,
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.port_ops = &sc1200_port_ops,
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.dma_ops = &sc1200_dma_ops,
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.host_flags = IDE_HFLAG_SERIALIZE |
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IDE_HFLAG_POST_SET_MODE |
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IDE_HFLAG_ABUSE_DMA_MODES,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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};
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static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct sc1200_saved_state *ss = NULL;
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int rc;
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#ifdef CONFIG_PM
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ss = kmalloc(sizeof(*ss), GFP_KERNEL);
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if (ss == NULL)
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return -ENOMEM;
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#endif
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rc = ide_pci_init_one(dev, &sc1200_chipset, ss);
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if (rc)
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kfree(ss);
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return rc;
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}
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static const struct pci_device_id sc1200_pci_tbl[] = {
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{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
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static struct pci_driver sc1200_pci_driver = {
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.name = "SC1200_IDE",
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.id_table = sc1200_pci_tbl,
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.probe = sc1200_init_one,
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.remove = ide_pci_remove,
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#ifdef CONFIG_PM
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.suspend = sc1200_suspend,
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.resume = sc1200_resume,
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#endif
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};
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static int __init sc1200_ide_init(void)
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{
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return ide_pci_register_driver(&sc1200_pci_driver);
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}
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static void __exit sc1200_ide_exit(void)
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{
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pci_unregister_driver(&sc1200_pci_driver);
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}
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module_init(sc1200_ide_init);
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module_exit(sc1200_ide_exit);
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MODULE_AUTHOR("Mark Lord");
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MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
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MODULE_LICENSE("GPL");
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