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![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
762 lines
16 KiB
C
762 lines
16 KiB
C
/*
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* drivers/pcmcia/m32r_pcc.c
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*
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* Device driver for the PCMCIA functionality of M32R.
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*
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* Copyright (c) 2001, 2002, 2003, 2004
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* Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/fcntl.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/timer.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/addrspace.h>
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#include <pcmcia/cs_types.h>
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#include <pcmcia/ss.h>
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#include <pcmcia/cs.h>
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/* XXX: should be moved into asm/irq.h */
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#define PCC0_IRQ 24
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#define PCC1_IRQ 25
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#include "m32r_pcc.h"
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#define CHAOS_PCC_DEBUG
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#ifdef CHAOS_PCC_DEBUG
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static volatile u_short dummy_readbuf;
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#endif
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#define PCC_DEBUG_DBEX
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/* Poll status interval -- 0 means default to interrupt */
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static int poll_interval = 0;
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typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
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typedef struct pcc_socket {
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u_short type, flags;
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struct pcmcia_socket socket;
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unsigned int number;
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unsigned int ioaddr;
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u_long mapaddr;
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u_long base; /* PCC register base */
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u_char cs_irq, intr;
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pccard_io_map io_map[MAX_IO_WIN];
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pccard_mem_map mem_map[MAX_WIN];
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u_char io_win;
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u_char mem_win;
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pcc_as_t current_space;
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u_char last_iodbex;
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#ifdef CHAOS_PCC_DEBUG
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u_char last_iosize;
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#endif
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#ifdef CONFIG_PROC_FS
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struct proc_dir_entry *proc;
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#endif
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} pcc_socket_t;
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static int pcc_sockets = 0;
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static pcc_socket_t socket[M32R_MAX_PCC] = {
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{ 0, }, /* ... */
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};
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/*====================================================================*/
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static unsigned int pcc_get(u_short, unsigned int);
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static void pcc_set(u_short, unsigned int , unsigned int );
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static DEFINE_SPINLOCK(pcc_lock);
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void pcc_iorw(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int wr, int flag)
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{
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u_long addr;
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u_long flags;
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int need_ex;
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#ifdef PCC_DEBUG_DBEX
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int _dbex;
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#endif
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pcc_socket_t *t = &socket[sock];
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#ifdef CHAOS_PCC_DEBUG
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int map_changed = 0;
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#endif
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/* Need lock ? */
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spin_lock_irqsave(&pcc_lock, flags);
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/*
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* Check if need dbex
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*/
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need_ex = (size > 1 && flag == 0) ? PCMOD_DBEX : 0;
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#ifdef PCC_DEBUG_DBEX
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_dbex = need_ex;
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need_ex = 0;
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#endif
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/*
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* calculate access address
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*/
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addr = t->mapaddr + port - t->ioaddr + KSEG1; /* XXX */
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/*
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* Check current mapping
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*/
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if (t->current_space != as_io || t->last_iodbex != need_ex) {
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u_long cbsz;
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/*
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* Disable first
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*/
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pcc_set(sock, PCCR, 0);
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/*
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* Set mode and io address
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*/
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cbsz = (t->flags & MAP_16BIT) ? 0 : PCMOD_CBSZ;
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pcc_set(sock, PCMOD, PCMOD_AS_IO | cbsz | need_ex);
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pcc_set(sock, PCADR, addr & 0x1ff00000);
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/*
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* Enable and read it
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*/
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pcc_set(sock, PCCR, 1);
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#ifdef CHAOS_PCC_DEBUG
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#if 0
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map_changed = (t->current_space == as_attr && size == 2); /* XXX */
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#else
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map_changed = 1;
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#endif
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#endif
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t->current_space = as_io;
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}
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/*
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* access to IO space
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*/
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if (size == 1) {
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/* Byte */
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unsigned char *bp = (unsigned char *)buf;
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#ifdef CHAOS_DEBUG
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if (map_changed) {
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dummy_readbuf = readb(addr);
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}
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#endif
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if (wr) {
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/* write Byte */
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while (nmemb--) {
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writeb(*bp++, addr);
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}
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} else {
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/* read Byte */
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while (nmemb--) {
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*bp++ = readb(addr);
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}
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}
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} else {
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/* Word */
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unsigned short *bp = (unsigned short *)buf;
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#ifdef CHAOS_PCC_DEBUG
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if (map_changed) {
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dummy_readbuf = readw(addr);
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}
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#endif
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if (wr) {
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/* write Word */
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while (nmemb--) {
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#ifdef PCC_DEBUG_DBEX
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if (_dbex) {
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unsigned char *cp = (unsigned char *)bp;
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unsigned short tmp;
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tmp = cp[1] << 8 | cp[0];
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writew(tmp, addr);
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bp++;
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} else
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#endif
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writew(*bp++, addr);
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}
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} else {
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/* read Word */
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while (nmemb--) {
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#ifdef PCC_DEBUG_DBEX
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if (_dbex) {
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unsigned char *cp = (unsigned char *)bp;
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unsigned short tmp;
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tmp = readw(addr);
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cp[0] = tmp & 0xff;
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cp[1] = (tmp >> 8) & 0xff;
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bp++;
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} else
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#endif
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*bp++ = readw(addr);
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}
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}
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}
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#if 1
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/* addr is no longer used */
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if ((addr = pcc_get(sock, PCIRC)) & PCIRC_BWERR) {
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printk("m32r_pcc: BWERR detected : port 0x%04lx : iosize %dbit\n",
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port, size * 8);
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pcc_set(sock, PCIRC, addr);
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}
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#endif
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/*
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* save state
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*/
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t->last_iosize = size;
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t->last_iodbex = need_ex;
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/* Need lock ? */
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spin_unlock_irqrestore(&pcc_lock,flags);
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return;
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}
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void pcc_ioread(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
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pcc_iorw(sock, port, buf, size, nmemb, 0, flag);
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}
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void pcc_iowrite(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
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pcc_iorw(sock, port, buf, size, nmemb, 1, flag);
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}
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/*====================================================================*/
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#define IS_REGISTERED 0x2000
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#define IS_ALIVE 0x8000
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typedef struct pcc_t {
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char *name;
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u_short flags;
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} pcc_t;
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static pcc_t pcc[] = {
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{ "xnux2", 0 }, { "xnux2", 0 },
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};
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static irqreturn_t pcc_interrupt(int, void *);
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/*====================================================================*/
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static struct timer_list poll_timer;
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static unsigned int pcc_get(u_short sock, unsigned int reg)
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{
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return inl(socket[sock].base + reg);
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}
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static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
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{
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outl(data, socket[sock].base + reg);
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}
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/*======================================================================
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See if a card is present, powered up, in IO mode, and already
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bound to a (non PC Card) Linux driver. We leave these alone.
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We make an exception for cards that seem to be serial devices.
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======================================================================*/
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static int __init is_alive(u_short sock)
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{
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unsigned int stat;
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unsigned int f;
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stat = pcc_get(sock, PCIRC);
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f = (stat & (PCIRC_CDIN1 | PCIRC_CDIN2)) >> 16;
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if(!f){
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printk("m32r_pcc: No Card is detected at socket %d : stat = 0x%08x\n",stat,sock);
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return 0;
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}
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if(f!=3)
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printk("m32r_pcc: Insertion fail (%.8x) at socket %d\n",stat,sock);
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else
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printk("m32r_pcc: Card is Inserted at socket %d(%.8x)\n",sock,stat);
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return 0;
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}
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static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
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unsigned int ioaddr)
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{
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pcc_socket_t *t = &socket[pcc_sockets];
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/* add sockets */
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t->ioaddr = ioaddr;
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t->mapaddr = mapaddr;
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t->base = base;
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#ifdef CHAOS_PCC_DEBUG
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t->flags = MAP_16BIT;
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#else
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t->flags = 0;
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#endif
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if (is_alive(pcc_sockets))
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t->flags |= IS_ALIVE;
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/* add pcc */
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if (t->base > 0) {
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request_region(t->base, 0x20, "m32r-pcc");
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}
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printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
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printk("pcc at 0x%08lx\n", t->base);
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/* Update socket interrupt information, capabilities */
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t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
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t->socket.map_size = M32R_PCC_MAPSIZE;
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t->socket.io_offset = ioaddr; /* use for io access offset */
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t->socket.irq_mask = 0;
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t->socket.pci_irq = 2 + pcc_sockets; /* XXX */
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request_irq(irq, pcc_interrupt, 0, "m32r-pcc", pcc_interrupt);
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pcc_sockets++;
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return;
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}
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/*====================================================================*/
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static irqreturn_t pcc_interrupt(int irq, void *dev)
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{
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int i, j, irc;
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u_int events, active;
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int handled = 0;
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pr_debug("m32r_pcc: pcc_interrupt(%d)\n", irq);
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for (j = 0; j < 20; j++) {
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active = 0;
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for (i = 0; i < pcc_sockets; i++) {
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if ((socket[i].cs_irq != irq) &&
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(socket[i].socket.pci_irq != irq))
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continue;
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handled = 1;
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irc = pcc_get(i, PCIRC);
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irc >>=16;
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pr_debug("m32r_pcc: interrupt: socket %d pcirc 0x%02x ",
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i, irc);
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if (!irc)
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continue;
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events = (irc) ? SS_DETECT : 0;
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events |= (pcc_get(i,PCCR) & PCCR_PCEN) ? SS_READY : 0;
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pr_debug("m32r_pcc: event 0x%02x\n", events);
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if (events)
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pcmcia_parse_events(&socket[i].socket, events);
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active |= events;
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active = 0;
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}
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if (!active) break;
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}
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if (j == 20)
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printk(KERN_NOTICE "m32r-pcc: infinite loop in interrupt handler\n");
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pr_debug("m32r_pcc: interrupt done\n");
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return IRQ_RETVAL(handled);
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} /* pcc_interrupt */
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static void pcc_interrupt_wrapper(u_long data)
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{
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pcc_interrupt(0, NULL);
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init_timer(&poll_timer);
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poll_timer.expires = jiffies + poll_interval;
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add_timer(&poll_timer);
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}
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/*====================================================================*/
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static int _pcc_get_status(u_short sock, u_int *value)
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{
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u_int status;
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status = pcc_get(sock,PCIRC);
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*value = ((status & PCIRC_CDIN1) && (status & PCIRC_CDIN2))
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? SS_DETECT : 0;
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status = pcc_get(sock,PCCR);
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#if 0
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*value |= (status & PCCR_PCEN) ? SS_READY : 0;
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#else
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*value |= SS_READY; /* XXX: always */
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#endif
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status = pcc_get(sock,PCCSIGCR);
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*value |= (status & PCCSIGCR_VEN) ? SS_POWERON : 0;
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pr_debug("m32r_pcc: GetStatus(%d) = %#4.4x\n", sock, *value);
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return 0;
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} /* _get_status */
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/*====================================================================*/
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static int _pcc_set_socket(u_short sock, socket_state_t *state)
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{
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u_long reg = 0;
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pr_debug("m32r_pcc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
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"io_irq %d, csc_mask %#2.2x)", sock, state->flags,
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state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
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if (state->Vcc) {
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/*
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* 5V only
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*/
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if (state->Vcc == 50) {
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reg |= PCCSIGCR_VEN;
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} else {
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return -EINVAL;
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}
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}
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if (state->flags & SS_RESET) {
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pr_debug("m32r_pcc: :RESET\n");
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reg |= PCCSIGCR_CRST;
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}
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if (state->flags & SS_OUTPUT_ENA){
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pr_debug("m32r_pcc: :OUTPUT_ENA\n");
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/* bit clear */
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} else {
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reg |= PCCSIGCR_SEN;
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}
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pcc_set(sock,PCCSIGCR,reg);
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if(state->flags & SS_IOCARD){
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pr_debug("m32r_pcc: :IOCARD");
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}
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if (state->flags & SS_PWR_AUTO) {
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pr_debug("m32r_pcc: :PWR_AUTO");
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}
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if (state->csc_mask & SS_DETECT)
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pr_debug("m32r_pcc: :csc-SS_DETECT");
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if (state->flags & SS_IOCARD) {
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if (state->csc_mask & SS_STSCHG)
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pr_debug("m32r_pcc: :STSCHG");
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} else {
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if (state->csc_mask & SS_BATDEAD)
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pr_debug("m32r_pcc: :BATDEAD");
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if (state->csc_mask & SS_BATWARN)
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pr_debug("m32r_pcc: :BATWARN");
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if (state->csc_mask & SS_READY)
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pr_debug("m32r_pcc: :READY");
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}
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pr_debug("m32r_pcc: \n");
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return 0;
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} /* _set_socket */
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/*====================================================================*/
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static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
|
|
{
|
|
u_char map;
|
|
|
|
pr_debug("m32r_pcc: SetIOMap(%d, %d, %#2.2x, %d ns, "
|
|
"%#llx-%#llx)\n", sock, io->map, io->flags,
|
|
io->speed, (unsigned long long)io->start,
|
|
(unsigned long long)io->stop);
|
|
map = io->map;
|
|
|
|
return 0;
|
|
} /* _set_io_map */
|
|
|
|
/*====================================================================*/
|
|
|
|
static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
|
|
{
|
|
|
|
u_char map = mem->map;
|
|
u_long mode;
|
|
u_long addr;
|
|
pcc_socket_t *t = &socket[sock];
|
|
#ifdef CHAOS_PCC_DEBUG
|
|
#if 0
|
|
pcc_as_t last = t->current_space;
|
|
#endif
|
|
#endif
|
|
|
|
pr_debug("m32r_pcc: SetMemMap(%d, %d, %#2.2x, %d ns, "
|
|
"%#llx, %#x)\n", sock, map, mem->flags,
|
|
mem->speed, (unsigned long long)mem->static_start,
|
|
mem->card_start);
|
|
|
|
/*
|
|
* sanity check
|
|
*/
|
|
if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* de-activate
|
|
*/
|
|
if ((mem->flags & MAP_ACTIVE) == 0) {
|
|
t->current_space = as_none;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Disable first
|
|
*/
|
|
pcc_set(sock, PCCR, 0);
|
|
|
|
/*
|
|
* Set mode
|
|
*/
|
|
if (mem->flags & MAP_ATTRIB) {
|
|
mode = PCMOD_AS_ATTRIB | PCMOD_CBSZ;
|
|
t->current_space = as_attr;
|
|
} else {
|
|
mode = 0; /* common memory */
|
|
t->current_space = as_comm;
|
|
}
|
|
pcc_set(sock, PCMOD, mode);
|
|
|
|
/*
|
|
* Set address
|
|
*/
|
|
addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
|
|
pcc_set(sock, PCADR, addr);
|
|
|
|
mem->static_start = addr + mem->card_start;
|
|
|
|
/*
|
|
* Enable again
|
|
*/
|
|
pcc_set(sock, PCCR, 1);
|
|
|
|
#ifdef CHAOS_PCC_DEBUG
|
|
#if 0
|
|
if (last != as_attr) {
|
|
#else
|
|
if (1) {
|
|
#endif
|
|
dummy_readbuf = *(u_char *)(addr + KSEG1);
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
} /* _set_mem_map */
|
|
|
|
#if 0 /* driver model ordering issue */
|
|
/*======================================================================
|
|
|
|
Routines for accessing socket information and register dumps via
|
|
/proc/bus/pccard/...
|
|
|
|
======================================================================*/
|
|
|
|
static ssize_t show_info(struct class_device *class_dev, char *buf)
|
|
{
|
|
pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
|
|
socket.dev);
|
|
|
|
return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
|
|
pcc[s->type].name, s->base);
|
|
}
|
|
|
|
static ssize_t show_exca(struct class_device *class_dev, char *buf)
|
|
{
|
|
/* FIXME */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
|
|
static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
|
|
#endif
|
|
|
|
/*====================================================================*/
|
|
|
|
/* this is horribly ugly... proper locking needs to be done here at
|
|
* some time... */
|
|
#define LOCKED(x) do { \
|
|
int retval; \
|
|
unsigned long flags; \
|
|
spin_lock_irqsave(&pcc_lock, flags); \
|
|
retval = x; \
|
|
spin_unlock_irqrestore(&pcc_lock, flags); \
|
|
return retval; \
|
|
} while (0)
|
|
|
|
|
|
static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
|
|
{
|
|
unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
|
|
|
|
if (socket[sock].flags & IS_ALIVE) {
|
|
*value = 0;
|
|
return -EINVAL;
|
|
}
|
|
LOCKED(_pcc_get_status(sock, value));
|
|
}
|
|
|
|
static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
|
|
{
|
|
unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
|
|
|
|
if (socket[sock].flags & IS_ALIVE)
|
|
return -EINVAL;
|
|
|
|
LOCKED(_pcc_set_socket(sock, state));
|
|
}
|
|
|
|
static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
|
|
{
|
|
unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
|
|
|
|
if (socket[sock].flags & IS_ALIVE)
|
|
return -EINVAL;
|
|
LOCKED(_pcc_set_io_map(sock, io));
|
|
}
|
|
|
|
static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
|
|
{
|
|
unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
|
|
|
|
if (socket[sock].flags & IS_ALIVE)
|
|
return -EINVAL;
|
|
LOCKED(_pcc_set_mem_map(sock, mem));
|
|
}
|
|
|
|
static int pcc_init(struct pcmcia_socket *s)
|
|
{
|
|
pr_debug("m32r_pcc: init call\n");
|
|
return 0;
|
|
}
|
|
|
|
static struct pccard_operations pcc_operations = {
|
|
.init = pcc_init,
|
|
.get_status = pcc_get_status,
|
|
.set_socket = pcc_set_socket,
|
|
.set_io_map = pcc_set_io_map,
|
|
.set_mem_map = pcc_set_mem_map,
|
|
};
|
|
|
|
/*====================================================================*/
|
|
|
|
static struct platform_driver pcc_driver = {
|
|
.driver = {
|
|
.name = "pcc",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static struct platform_device pcc_device = {
|
|
.name = "pcc",
|
|
.id = 0,
|
|
};
|
|
|
|
/*====================================================================*/
|
|
|
|
static int __init init_m32r_pcc(void)
|
|
{
|
|
int i, ret;
|
|
|
|
ret = platform_driver_register(&pcc_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_device_register(&pcc_device);
|
|
if (ret){
|
|
platform_driver_unregister(&pcc_driver);
|
|
return ret;
|
|
}
|
|
|
|
printk(KERN_INFO "m32r PCC probe:\n");
|
|
|
|
pcc_sockets = 0;
|
|
|
|
add_pcc_socket(M32R_PCC0_BASE, PCC0_IRQ, M32R_PCC0_MAPBASE, 0x1000);
|
|
|
|
#ifdef CONFIG_M32RPCC_SLOT2
|
|
add_pcc_socket(M32R_PCC1_BASE, PCC1_IRQ, M32R_PCC1_MAPBASE, 0x2000);
|
|
#endif
|
|
|
|
if (pcc_sockets == 0) {
|
|
printk("socket is not found.\n");
|
|
platform_device_unregister(&pcc_device);
|
|
platform_driver_unregister(&pcc_driver);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Set up interrupt handler(s) */
|
|
|
|
for (i = 0 ; i < pcc_sockets ; i++) {
|
|
socket[i].socket.dev.parent = &pcc_device.dev;
|
|
socket[i].socket.ops = &pcc_operations;
|
|
socket[i].socket.resource_ops = &pccard_static_ops;
|
|
socket[i].socket.owner = THIS_MODULE;
|
|
socket[i].number = i;
|
|
ret = pcmcia_register_socket(&socket[i].socket);
|
|
if (!ret)
|
|
socket[i].flags |= IS_REGISTERED;
|
|
|
|
#if 0 /* driver model ordering issue */
|
|
class_device_create_file(&socket[i].socket.dev,
|
|
&class_device_attr_info);
|
|
class_device_create_file(&socket[i].socket.dev,
|
|
&class_device_attr_exca);
|
|
#endif
|
|
}
|
|
|
|
/* Finally, schedule a polling interrupt */
|
|
if (poll_interval != 0) {
|
|
poll_timer.function = pcc_interrupt_wrapper;
|
|
poll_timer.data = 0;
|
|
init_timer(&poll_timer);
|
|
poll_timer.expires = jiffies + poll_interval;
|
|
add_timer(&poll_timer);
|
|
}
|
|
|
|
return 0;
|
|
} /* init_m32r_pcc */
|
|
|
|
static void __exit exit_m32r_pcc(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < pcc_sockets; i++)
|
|
if (socket[i].flags & IS_REGISTERED)
|
|
pcmcia_unregister_socket(&socket[i].socket);
|
|
|
|
platform_device_unregister(&pcc_device);
|
|
if (poll_interval != 0)
|
|
del_timer_sync(&poll_timer);
|
|
|
|
platform_driver_unregister(&pcc_driver);
|
|
} /* exit_m32r_pcc */
|
|
|
|
module_init(init_m32r_pcc);
|
|
module_exit(exit_m32r_pcc);
|
|
MODULE_LICENSE("Dual MPL/GPL");
|
|
/*====================================================================*/
|