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![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
924 lines
23 KiB
C
924 lines
23 KiB
C
/*
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* Driver for Atmel AT32 and AT91 SPI Controllers
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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#include <mach/board.h>
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#include <mach/gpio.h>
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#include <mach/cpu.h>
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#include "atmel_spi.h"
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/*
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* The core SPI transfer engine just talks to a register bank to set up
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* DMA transfers; transfer queue progress is driven by IRQs. The clock
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* framework provides the base clock, subdivided for each spi_device.
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*/
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struct atmel_spi {
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spinlock_t lock;
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void __iomem *regs;
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int irq;
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struct clk *clk;
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struct platform_device *pdev;
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struct spi_device *stay;
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u8 stopping;
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struct list_head queue;
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struct spi_transfer *current_transfer;
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unsigned long current_remaining_bytes;
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struct spi_transfer *next_transfer;
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unsigned long next_remaining_bytes;
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void *buffer;
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dma_addr_t buffer_dma;
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};
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/* Controller-specific per-slave state */
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struct atmel_spi_device {
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unsigned int npcs_pin;
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u32 csr;
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};
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#define BUFFER_SIZE PAGE_SIZE
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#define INVALID_DMA_ADDRESS 0xffffffff
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/*
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* Version 2 of the SPI controller has
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* - CR.LASTXFER
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* - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
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* - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
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* - SPI_CSRx.CSAAT
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* - SPI_CSRx.SBCR allows faster clocking
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*
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* We can determine the controller version by reading the VERSION
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* register, but I haven't checked that it exists on all chips, and
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* this is cheaper anyway.
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*/
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static bool atmel_spi_is_v2(void)
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{
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return !cpu_is_at91rm9200();
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}
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/*
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* Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
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* they assume that spi slave device state will not change on deselect, so
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* that automagic deselection is OK. ("NPCSx rises if no data is to be
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* transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
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* controllers have CSAAT and friends.
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*
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* Since the CSAAT functionality is a bit weird on newer controllers as
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* well, we use GPIO to control nCSx pins on all controllers, updating
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* MR.PCS to avoid confusing the controller. Using GPIOs also lets us
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* support active-high chipselects despite the controller's belief that
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* only active-low devices/systems exists.
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*
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* However, at91rm9200 has a second erratum whereby nCS0 doesn't work
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* right when driven with GPIO. ("Mode Fault does not allow more than one
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* Master on Chip Select 0.") No workaround exists for that ... so for
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* nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
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* and (c) will trigger that first erratum in some cases.
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*
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* TODO: Test if the atmel_spi_is_v2() branch below works on
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* AT91RM9200 if we use some other register than CSR0. However, don't
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* do this unconditionally since AP7000 has an errata where the BITS
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* field in CSR0 overrides all other CSRs.
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*/
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static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
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{
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struct atmel_spi_device *asd = spi->controller_state;
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unsigned active = spi->mode & SPI_CS_HIGH;
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u32 mr;
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if (atmel_spi_is_v2()) {
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/*
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* Always use CSR0. This ensures that the clock
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* switches to the correct idle polarity before we
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* toggle the CS.
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*/
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spi_writel(as, CSR0, asd->csr);
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spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
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| SPI_BIT(MSTR));
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mr = spi_readl(as, MR);
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gpio_set_value(asd->npcs_pin, active);
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} else {
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u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
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int i;
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u32 csr;
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/* Make sure clock polarity is correct */
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for (i = 0; i < spi->master->num_chipselect; i++) {
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csr = spi_readl(as, CSR0 + 4 * i);
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if ((csr ^ cpol) & SPI_BIT(CPOL))
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spi_writel(as, CSR0 + 4 * i,
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csr ^ SPI_BIT(CPOL));
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}
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mr = spi_readl(as, MR);
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mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
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if (spi->chip_select != 0)
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gpio_set_value(asd->npcs_pin, active);
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spi_writel(as, MR, mr);
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}
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dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
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asd->npcs_pin, active ? " (high)" : "",
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mr);
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}
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static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
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{
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struct atmel_spi_device *asd = spi->controller_state;
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unsigned active = spi->mode & SPI_CS_HIGH;
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u32 mr;
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/* only deactivate *this* device; sometimes transfers to
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* another device may be active when this routine is called.
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*/
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mr = spi_readl(as, MR);
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if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
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mr = SPI_BFINS(PCS, 0xf, mr);
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spi_writel(as, MR, mr);
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}
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dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
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asd->npcs_pin, active ? " (low)" : "",
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mr);
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if (atmel_spi_is_v2() || spi->chip_select != 0)
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gpio_set_value(asd->npcs_pin, !active);
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}
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static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
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struct spi_transfer *xfer)
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{
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return msg->transfers.prev == &xfer->transfer_list;
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}
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static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
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{
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return xfer->delay_usecs == 0 && !xfer->cs_change;
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}
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static void atmel_spi_next_xfer_data(struct spi_master *master,
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struct spi_transfer *xfer,
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dma_addr_t *tx_dma,
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dma_addr_t *rx_dma,
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u32 *plen)
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{
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struct atmel_spi *as = spi_master_get_devdata(master);
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u32 len = *plen;
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/* use scratch buffer only when rx or tx data is unspecified */
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if (xfer->rx_buf)
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*rx_dma = xfer->rx_dma + xfer->len - *plen;
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else {
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*rx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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len = BUFFER_SIZE;
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}
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if (xfer->tx_buf)
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*tx_dma = xfer->tx_dma + xfer->len - *plen;
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else {
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*tx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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len = BUFFER_SIZE;
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memset(as->buffer, 0, len);
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dma_sync_single_for_device(&as->pdev->dev,
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as->buffer_dma, len, DMA_TO_DEVICE);
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}
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*plen = len;
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}
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/*
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* Submit next transfer for DMA.
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* lock is held, spi irq is blocked
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*/
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static void atmel_spi_next_xfer(struct spi_master *master,
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struct spi_message *msg)
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{
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_transfer *xfer;
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u32 len, remaining;
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u32 ieval;
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dma_addr_t tx_dma, rx_dma;
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if (!as->current_transfer)
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xfer = list_entry(msg->transfers.next,
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struct spi_transfer, transfer_list);
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else if (!as->next_transfer)
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xfer = list_entry(as->current_transfer->transfer_list.next,
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struct spi_transfer, transfer_list);
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else
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xfer = NULL;
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if (xfer) {
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spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
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len = xfer->len;
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atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
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remaining = xfer->len - len;
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spi_writel(as, RPR, rx_dma);
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spi_writel(as, TPR, tx_dma);
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if (msg->spi->bits_per_word > 8)
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len >>= 1;
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spi_writel(as, RCR, len);
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spi_writel(as, TCR, len);
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dev_dbg(&msg->spi->dev,
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" start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
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xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
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xfer->rx_buf, xfer->rx_dma);
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} else {
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xfer = as->next_transfer;
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remaining = as->next_remaining_bytes;
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}
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as->current_transfer = xfer;
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as->current_remaining_bytes = remaining;
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if (remaining > 0)
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len = remaining;
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else if (!atmel_spi_xfer_is_last(msg, xfer)
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&& atmel_spi_xfer_can_be_chained(xfer)) {
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xfer = list_entry(xfer->transfer_list.next,
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struct spi_transfer, transfer_list);
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len = xfer->len;
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} else
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xfer = NULL;
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as->next_transfer = xfer;
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if (xfer) {
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u32 total;
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total = len;
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atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
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as->next_remaining_bytes = total - len;
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spi_writel(as, RNPR, rx_dma);
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spi_writel(as, TNPR, tx_dma);
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if (msg->spi->bits_per_word > 8)
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len >>= 1;
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spi_writel(as, RNCR, len);
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spi_writel(as, TNCR, len);
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dev_dbg(&msg->spi->dev,
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" next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
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xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
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xfer->rx_buf, xfer->rx_dma);
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ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
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} else {
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spi_writel(as, RNCR, 0);
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spi_writel(as, TNCR, 0);
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ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
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}
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/* REVISIT: We're waiting for ENDRX before we start the next
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* transfer because we need to handle some difficult timing
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* issues otherwise. If we wait for ENDTX in one transfer and
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* then starts waiting for ENDRX in the next, it's difficult
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* to tell the difference between the ENDRX interrupt we're
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* actually waiting for and the ENDRX interrupt of the
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* previous transfer.
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*
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* It should be doable, though. Just not now...
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*/
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spi_writel(as, IER, ieval);
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spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
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}
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static void atmel_spi_next_message(struct spi_master *master)
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{
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_message *msg;
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struct spi_device *spi;
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BUG_ON(as->current_transfer);
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msg = list_entry(as->queue.next, struct spi_message, queue);
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spi = msg->spi;
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dev_dbg(master->dev.parent, "start message %p for %s\n",
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msg, dev_name(&spi->dev));
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/* select chip if it's not still active */
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if (as->stay) {
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if (as->stay != spi) {
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cs_deactivate(as, as->stay);
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cs_activate(as, spi);
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}
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as->stay = NULL;
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} else
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cs_activate(as, spi);
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atmel_spi_next_xfer(master, msg);
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}
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/*
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* For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
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* - The buffer is either valid for CPU access, else NULL
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* - If the buffer is valid, so is its DMA addresss
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*
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* This driver manages the dma addresss unless message->is_dma_mapped.
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*/
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static int
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atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
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{
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struct device *dev = &as->pdev->dev;
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xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
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if (xfer->tx_buf) {
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xfer->tx_dma = dma_map_single(dev,
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(void *) xfer->tx_buf, xfer->len,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, xfer->tx_dma))
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return -ENOMEM;
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}
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if (xfer->rx_buf) {
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xfer->rx_dma = dma_map_single(dev,
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xfer->rx_buf, xfer->len,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, xfer->rx_dma)) {
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if (xfer->tx_buf)
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dma_unmap_single(dev,
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xfer->tx_dma, xfer->len,
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DMA_TO_DEVICE);
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return -ENOMEM;
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}
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}
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return 0;
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}
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static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
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struct spi_transfer *xfer)
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{
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if (xfer->tx_dma != INVALID_DMA_ADDRESS)
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dma_unmap_single(master->dev.parent, xfer->tx_dma,
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xfer->len, DMA_TO_DEVICE);
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if (xfer->rx_dma != INVALID_DMA_ADDRESS)
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dma_unmap_single(master->dev.parent, xfer->rx_dma,
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xfer->len, DMA_FROM_DEVICE);
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}
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static void
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atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
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struct spi_message *msg, int status, int stay)
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{
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if (!stay || status < 0)
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cs_deactivate(as, msg->spi);
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else
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as->stay = msg->spi;
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list_del(&msg->queue);
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msg->status = status;
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dev_dbg(master->dev.parent,
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"xfer complete: %u bytes transferred\n",
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msg->actual_length);
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spin_unlock(&as->lock);
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msg->complete(msg->context);
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spin_lock(&as->lock);
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as->current_transfer = NULL;
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as->next_transfer = NULL;
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/* continue if needed */
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if (list_empty(&as->queue) || as->stopping)
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spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
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else
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atmel_spi_next_message(master);
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}
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static irqreturn_t
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atmel_spi_interrupt(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_message *msg;
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struct spi_transfer *xfer;
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u32 status, pending, imr;
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int ret = IRQ_NONE;
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spin_lock(&as->lock);
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|
|
xfer = as->current_transfer;
|
|
msg = list_entry(as->queue.next, struct spi_message, queue);
|
|
|
|
imr = spi_readl(as, IMR);
|
|
status = spi_readl(as, SR);
|
|
pending = status & imr;
|
|
|
|
if (pending & SPI_BIT(OVRES)) {
|
|
int timeout;
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
|
|
| SPI_BIT(OVRES)));
|
|
|
|
/*
|
|
* When we get an overrun, we disregard the current
|
|
* transfer. Data will not be copied back from any
|
|
* bounce buffer and msg->actual_len will not be
|
|
* updated with the last xfer.
|
|
*
|
|
* We will also not process any remaning transfers in
|
|
* the message.
|
|
*
|
|
* First, stop the transfer and unmap the DMA buffers.
|
|
*/
|
|
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
|
|
if (!msg->is_dma_mapped)
|
|
atmel_spi_dma_unmap_xfer(master, xfer);
|
|
|
|
/* REVISIT: udelay in irq is unfriendly */
|
|
if (xfer->delay_usecs)
|
|
udelay(xfer->delay_usecs);
|
|
|
|
dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
|
|
spi_readl(as, TCR), spi_readl(as, RCR));
|
|
|
|
/*
|
|
* Clean up DMA registers and make sure the data
|
|
* registers are empty.
|
|
*/
|
|
spi_writel(as, RNCR, 0);
|
|
spi_writel(as, TNCR, 0);
|
|
spi_writel(as, RCR, 0);
|
|
spi_writel(as, TCR, 0);
|
|
for (timeout = 1000; timeout; timeout--)
|
|
if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
|
|
break;
|
|
if (!timeout)
|
|
dev_warn(master->dev.parent,
|
|
"timeout waiting for TXEMPTY");
|
|
while (spi_readl(as, SR) & SPI_BIT(RDRF))
|
|
spi_readl(as, RDR);
|
|
|
|
/* Clear any overrun happening while cleaning up */
|
|
spi_readl(as, SR);
|
|
|
|
atmel_spi_msg_done(master, as, msg, -EIO, 0);
|
|
} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
|
|
ret = IRQ_HANDLED;
|
|
|
|
spi_writel(as, IDR, pending);
|
|
|
|
if (as->current_remaining_bytes == 0) {
|
|
msg->actual_length += xfer->len;
|
|
|
|
if (!msg->is_dma_mapped)
|
|
atmel_spi_dma_unmap_xfer(master, xfer);
|
|
|
|
/* REVISIT: udelay in irq is unfriendly */
|
|
if (xfer->delay_usecs)
|
|
udelay(xfer->delay_usecs);
|
|
|
|
if (atmel_spi_xfer_is_last(msg, xfer)) {
|
|
/* report completed message */
|
|
atmel_spi_msg_done(master, as, msg, 0,
|
|
xfer->cs_change);
|
|
} else {
|
|
if (xfer->cs_change) {
|
|
cs_deactivate(as, msg->spi);
|
|
udelay(1);
|
|
cs_activate(as, msg->spi);
|
|
}
|
|
|
|
/*
|
|
* Not done yet. Submit the next transfer.
|
|
*
|
|
* FIXME handle protocol options for xfer
|
|
*/
|
|
atmel_spi_next_xfer(master, msg);
|
|
}
|
|
} else {
|
|
/*
|
|
* Keep going, we still have data to send in
|
|
* the current transfer.
|
|
*/
|
|
atmel_spi_next_xfer(master, msg);
|
|
}
|
|
}
|
|
|
|
spin_unlock(&as->lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int atmel_spi_setup(struct spi_device *spi)
|
|
{
|
|
struct atmel_spi *as;
|
|
struct atmel_spi_device *asd;
|
|
u32 scbr, csr;
|
|
unsigned int bits = spi->bits_per_word;
|
|
unsigned long bus_hz;
|
|
unsigned int npcs_pin;
|
|
int ret;
|
|
|
|
as = spi_master_get_devdata(spi->master);
|
|
|
|
if (as->stopping)
|
|
return -ESHUTDOWN;
|
|
|
|
if (spi->chip_select > spi->master->num_chipselect) {
|
|
dev_dbg(&spi->dev,
|
|
"setup: invalid chipselect %u (%u defined)\n",
|
|
spi->chip_select, spi->master->num_chipselect);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (bits < 8 || bits > 16) {
|
|
dev_dbg(&spi->dev,
|
|
"setup: invalid bits_per_word %u (8 to 16)\n",
|
|
bits);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* see notes above re chipselect */
|
|
if (!atmel_spi_is_v2()
|
|
&& spi->chip_select == 0
|
|
&& (spi->mode & SPI_CS_HIGH)) {
|
|
dev_dbg(&spi->dev, "setup: can't be active-high\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* v1 chips start out at half the peripheral bus speed. */
|
|
bus_hz = clk_get_rate(as->clk);
|
|
if (!atmel_spi_is_v2())
|
|
bus_hz /= 2;
|
|
|
|
if (spi->max_speed_hz) {
|
|
/*
|
|
* Calculate the lowest divider that satisfies the
|
|
* constraint, assuming div32/fdiv/mbz == 0.
|
|
*/
|
|
scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
|
|
|
|
/*
|
|
* If the resulting divider doesn't fit into the
|
|
* register bitfield, we can't satisfy the constraint.
|
|
*/
|
|
if (scbr >= (1 << SPI_SCBR_SIZE)) {
|
|
dev_dbg(&spi->dev,
|
|
"setup: %d Hz too slow, scbr %u; min %ld Hz\n",
|
|
spi->max_speed_hz, scbr, bus_hz/255);
|
|
return -EINVAL;
|
|
}
|
|
} else
|
|
/* speed zero means "as slow as possible" */
|
|
scbr = 0xff;
|
|
|
|
csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
|
|
if (spi->mode & SPI_CPOL)
|
|
csr |= SPI_BIT(CPOL);
|
|
if (!(spi->mode & SPI_CPHA))
|
|
csr |= SPI_BIT(NCPHA);
|
|
|
|
/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
|
|
*
|
|
* DLYBCT would add delays between words, slowing down transfers.
|
|
* It could potentially be useful to cope with DMA bottlenecks, but
|
|
* in those cases it's probably best to just use a lower bitrate.
|
|
*/
|
|
csr |= SPI_BF(DLYBS, 0);
|
|
csr |= SPI_BF(DLYBCT, 0);
|
|
|
|
/* chipselect must have been muxed as GPIO (e.g. in board setup) */
|
|
npcs_pin = (unsigned int)spi->controller_data;
|
|
asd = spi->controller_state;
|
|
if (!asd) {
|
|
asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
|
|
if (!asd)
|
|
return -ENOMEM;
|
|
|
|
ret = gpio_request(npcs_pin, dev_name(&spi->dev));
|
|
if (ret) {
|
|
kfree(asd);
|
|
return ret;
|
|
}
|
|
|
|
asd->npcs_pin = npcs_pin;
|
|
spi->controller_state = asd;
|
|
gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
|
|
} else {
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&as->lock, flags);
|
|
if (as->stay == spi)
|
|
as->stay = NULL;
|
|
cs_deactivate(as, spi);
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
}
|
|
|
|
asd->csr = csr;
|
|
|
|
dev_dbg(&spi->dev,
|
|
"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
|
|
bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
|
|
|
|
if (!atmel_spi_is_v2())
|
|
spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
|
|
{
|
|
struct atmel_spi *as;
|
|
struct spi_transfer *xfer;
|
|
unsigned long flags;
|
|
struct device *controller = spi->master->dev.parent;
|
|
|
|
as = spi_master_get_devdata(spi->master);
|
|
|
|
dev_dbg(controller, "new message %p submitted for %s\n",
|
|
msg, dev_name(&spi->dev));
|
|
|
|
if (unlikely(list_empty(&msg->transfers)))
|
|
return -EINVAL;
|
|
|
|
if (as->stopping)
|
|
return -ESHUTDOWN;
|
|
|
|
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
|
|
if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
|
|
dev_dbg(&spi->dev, "missing rx or tx buf\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* FIXME implement these protocol options!! */
|
|
if (xfer->bits_per_word || xfer->speed_hz) {
|
|
dev_dbg(&spi->dev, "no protocol options yet\n");
|
|
return -ENOPROTOOPT;
|
|
}
|
|
|
|
/*
|
|
* DMA map early, for performance (empties dcache ASAP) and
|
|
* better fault reporting. This is a DMA-only driver.
|
|
*
|
|
* NOTE that if dma_unmap_single() ever starts to do work on
|
|
* platforms supported by this driver, we would need to clean
|
|
* up mappings for previously-mapped transfers.
|
|
*/
|
|
if (!msg->is_dma_mapped) {
|
|
if (atmel_spi_dma_map_xfer(as, xfer) < 0)
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
#ifdef VERBOSE
|
|
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
|
|
dev_dbg(controller,
|
|
" xfer %p: len %u tx %p/%08x rx %p/%08x\n",
|
|
xfer, xfer->len,
|
|
xfer->tx_buf, xfer->tx_dma,
|
|
xfer->rx_buf, xfer->rx_dma);
|
|
}
|
|
#endif
|
|
|
|
msg->status = -EINPROGRESS;
|
|
msg->actual_length = 0;
|
|
|
|
spin_lock_irqsave(&as->lock, flags);
|
|
list_add_tail(&msg->queue, &as->queue);
|
|
if (!as->current_transfer)
|
|
atmel_spi_next_message(spi->master);
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void atmel_spi_cleanup(struct spi_device *spi)
|
|
{
|
|
struct atmel_spi *as = spi_master_get_devdata(spi->master);
|
|
struct atmel_spi_device *asd = spi->controller_state;
|
|
unsigned gpio = (unsigned) spi->controller_data;
|
|
unsigned long flags;
|
|
|
|
if (!asd)
|
|
return;
|
|
|
|
spin_lock_irqsave(&as->lock, flags);
|
|
if (as->stay == spi) {
|
|
as->stay = NULL;
|
|
cs_deactivate(as, spi);
|
|
}
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
|
|
spi->controller_state = NULL;
|
|
gpio_free(gpio);
|
|
kfree(asd);
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
static int __init atmel_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *regs;
|
|
int irq;
|
|
struct clk *clk;
|
|
int ret;
|
|
struct spi_master *master;
|
|
struct atmel_spi *as;
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!regs)
|
|
return -ENXIO;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
clk = clk_get(&pdev->dev, "spi_clk");
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
/* setup spi core then atmel-specific driver state */
|
|
ret = -ENOMEM;
|
|
master = spi_alloc_master(&pdev->dev, sizeof *as);
|
|
if (!master)
|
|
goto out_free;
|
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
|
master->bus_num = pdev->id;
|
|
master->num_chipselect = 4;
|
|
master->setup = atmel_spi_setup;
|
|
master->transfer = atmel_spi_transfer;
|
|
master->cleanup = atmel_spi_cleanup;
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
as = spi_master_get_devdata(master);
|
|
|
|
/*
|
|
* Scratch buffer is used for throwaway rx and tx data.
|
|
* It's coherent to minimize dcache pollution.
|
|
*/
|
|
as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
|
|
&as->buffer_dma, GFP_KERNEL);
|
|
if (!as->buffer)
|
|
goto out_free;
|
|
|
|
spin_lock_init(&as->lock);
|
|
INIT_LIST_HEAD(&as->queue);
|
|
as->pdev = pdev;
|
|
as->regs = ioremap(regs->start, resource_size(regs));
|
|
if (!as->regs)
|
|
goto out_free_buffer;
|
|
as->irq = irq;
|
|
as->clk = clk;
|
|
|
|
ret = request_irq(irq, atmel_spi_interrupt, 0,
|
|
dev_name(&pdev->dev), master);
|
|
if (ret)
|
|
goto out_unmap_regs;
|
|
|
|
/* Initialize the hardware */
|
|
clk_enable(clk);
|
|
spi_writel(as, CR, SPI_BIT(SWRST));
|
|
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
|
|
spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
|
|
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
|
|
spi_writel(as, CR, SPI_BIT(SPIEN));
|
|
|
|
/* go! */
|
|
dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
|
|
(unsigned long)regs->start, irq);
|
|
|
|
ret = spi_register_master(master);
|
|
if (ret)
|
|
goto out_reset_hw;
|
|
|
|
return 0;
|
|
|
|
out_reset_hw:
|
|
spi_writel(as, CR, SPI_BIT(SWRST));
|
|
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
|
|
clk_disable(clk);
|
|
free_irq(irq, master);
|
|
out_unmap_regs:
|
|
iounmap(as->regs);
|
|
out_free_buffer:
|
|
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
|
|
as->buffer_dma);
|
|
out_free:
|
|
clk_put(clk);
|
|
spi_master_put(master);
|
|
return ret;
|
|
}
|
|
|
|
static int __exit atmel_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
struct spi_message *msg;
|
|
|
|
/* reset the hardware and block queue progress */
|
|
spin_lock_irq(&as->lock);
|
|
as->stopping = 1;
|
|
spi_writel(as, CR, SPI_BIT(SWRST));
|
|
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
|
|
spi_readl(as, SR);
|
|
spin_unlock_irq(&as->lock);
|
|
|
|
/* Terminate remaining queued transfers */
|
|
list_for_each_entry(msg, &as->queue, queue) {
|
|
/* REVISIT unmapping the dma is a NOP on ARM and AVR32
|
|
* but we shouldn't depend on that...
|
|
*/
|
|
msg->status = -ESHUTDOWN;
|
|
msg->complete(msg->context);
|
|
}
|
|
|
|
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
|
|
as->buffer_dma);
|
|
|
|
clk_disable(as->clk);
|
|
clk_put(as->clk);
|
|
free_irq(as->irq, master);
|
|
iounmap(as->regs);
|
|
|
|
spi_unregister_master(master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
clk_disable(as->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_spi_resume(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
clk_enable(as->clk);
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define atmel_spi_suspend NULL
|
|
#define atmel_spi_resume NULL
|
|
#endif
|
|
|
|
|
|
static struct platform_driver atmel_spi_driver = {
|
|
.driver = {
|
|
.name = "atmel_spi",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.suspend = atmel_spi_suspend,
|
|
.resume = atmel_spi_resume,
|
|
.remove = __exit_p(atmel_spi_remove),
|
|
};
|
|
|
|
static int __init atmel_spi_init(void)
|
|
{
|
|
return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
|
|
}
|
|
module_init(atmel_spi_init);
|
|
|
|
static void __exit atmel_spi_exit(void)
|
|
{
|
|
platform_driver_unregister(&atmel_spi_driver);
|
|
}
|
|
module_exit(atmel_spi_exit);
|
|
|
|
MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
|
|
MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:atmel_spi");
|