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The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, a video pipeline renderer (blender), an audio mixer and a DisplayPort source controller (transmitter). The DMA engine the provide data to the buffer manager, as well as the DisplayPort PHYs that drive the lanes, are external to the subsystem and interfaced using the DMA engine and PHY APIs respectively. This driver supports the DisplayPort Subsystem and implements - Two planes, for graphics and video - One CRTC that supports alpha blending - One encoder for the DisplayPort transmitter - One connector for an external monitor It currently doesn't support - Color keying - Test pattern generation - Audio - Live input from the Programmable Logic (FPGA) - Output to the Programmable Logic (FPGA) Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 lines
674 B
C
27 lines
674 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ZynqMP DisplayPort Driver
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*
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* Copyright (C) 2017 - 2020 Xilinx, Inc.
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*
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* Authors:
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* - Hyun Woo Kwon <hyun.kwon@xilinx.com>
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* - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef _ZYNQMP_DP_H_
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#define _ZYNQMP_DP_H_
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struct drm_device;
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struct platform_device;
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struct zynqmp_dp;
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struct zynqmp_dpsub;
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void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp);
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void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp);
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int zynqmp_dp_drm_init(struct zynqmp_dpsub *dpsub);
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int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm);
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void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub);
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#endif /* _ZYNQMP_DP_H_ */
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