345 lines
8.6 KiB
C
345 lines
8.6 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_jpeg.h"
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#include "amdgpu_pm.h"
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#include "soc15d.h"
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#include "soc15_common.h"
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#define JPEG_IDLE_TIMEOUT msecs_to_jiffies(1000)
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static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
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int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
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{
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int i, r;
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INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
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mutex_init(&adev->jpeg.jpeg_pg_lock);
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atomic_set(&adev->jpeg.total_submission_cnt, 0);
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if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
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(adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG))
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adev->jpeg.indirect_sram = true;
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for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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if (adev->jpeg.indirect_sram) {
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r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM |
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->jpeg.inst[i].dpg_sram_bo,
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&adev->jpeg.inst[i].dpg_sram_gpu_addr,
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&adev->jpeg.inst[i].dpg_sram_cpu_addr);
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if (r) {
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dev_err(adev->dev,
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"JPEG %d (%d) failed to allocate DPG bo\n", i, r);
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return r;
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}
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}
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}
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return 0;
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}
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int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
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{
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int i, j;
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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amdgpu_bo_free_kernel(
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&adev->jpeg.inst[i].dpg_sram_bo,
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&adev->jpeg.inst[i].dpg_sram_gpu_addr,
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(void **)&adev->jpeg.inst[i].dpg_sram_cpu_addr);
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
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amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);
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}
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mutex_destroy(&adev->jpeg.jpeg_pg_lock);
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return 0;
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}
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int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
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{
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cancel_delayed_work_sync(&adev->jpeg.idle_work);
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return 0;
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}
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int amdgpu_jpeg_resume(struct amdgpu_device *adev)
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{
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return 0;
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}
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static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
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{
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struct amdgpu_device *adev =
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container_of(work, struct amdgpu_device, jpeg.idle_work.work);
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unsigned int fences = 0;
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unsigned int i, j;
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i))
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continue;
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
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fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]);
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}
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if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt))
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
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AMD_PG_STATE_GATE);
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else
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schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
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}
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void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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atomic_inc(&adev->jpeg.total_submission_cnt);
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cancel_delayed_work_sync(&adev->jpeg.idle_work);
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mutex_lock(&adev->jpeg.jpeg_pg_lock);
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
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AMD_PG_STATE_UNGATE);
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mutex_unlock(&adev->jpeg.jpeg_pg_lock);
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}
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void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
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{
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atomic_dec(&ring->adev->jpeg.total_submission_cnt);
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schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
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}
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int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t tmp = 0;
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unsigned i;
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int r;
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/* JPEG in SRIOV does not support direct register read/write */
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if (amdgpu_sriov_vf(adev))
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return 0;
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r = amdgpu_ring_alloc(ring, 3);
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if (r)
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return r;
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WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
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/* Add a read register to make sure the write register is executed. */
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RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
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amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0));
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amdgpu_ring_write(ring, 0xABADCAFE);
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amdgpu_ring_commit(ring);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
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if (tmp == 0xABADCAFE)
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break;
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udelay(1);
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}
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if (i >= adev->usec_timeout)
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r = -ETIMEDOUT;
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return r;
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}
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static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
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struct dma_fence **fence)
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_job *job;
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struct amdgpu_ib *ib;
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struct dma_fence *f = NULL;
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const unsigned ib_size_dw = 16;
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int i, r;
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r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
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AMDGPU_IB_POOL_DIRECT, &job);
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if (r)
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return r;
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ib = &job->ibs[0];
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ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0);
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ib->ptr[1] = 0xDEADBEEF;
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for (i = 2; i < 16; i += 2) {
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ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
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ib->ptr[i+1] = 0;
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}
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ib->length_dw = 16;
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r = amdgpu_job_submit_direct(job, ring, &f);
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if (r)
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goto err;
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if (fence)
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*fence = dma_fence_get(f);
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dma_fence_put(f);
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return 0;
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err:
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amdgpu_job_free(job);
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return r;
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}
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int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t tmp = 0;
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unsigned i;
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struct dma_fence *fence = NULL;
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long r = 0;
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r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
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if (r)
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goto error;
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r = dma_fence_wait_timeout(fence, false, timeout);
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if (r == 0) {
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r = -ETIMEDOUT;
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goto error;
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} else if (r < 0) {
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goto error;
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} else {
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r = 0;
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}
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if (!amdgpu_sriov_vf(adev)) {
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
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if (tmp == 0xDEADBEEF)
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break;
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udelay(1);
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if (amdgpu_emu_mode == 1)
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udelay(10);
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}
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if (i >= adev->usec_timeout)
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r = -ETIMEDOUT;
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}
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dma_fence_put(fence);
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error:
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return r;
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}
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int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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struct ras_common_if *ras_if = adev->jpeg.ras_if;
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struct ras_dispatch_if ih_data = {
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.entry = entry,
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};
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if (!ras_if)
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return 0;
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ih_data.head = *ras_if;
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amdgpu_ras_interrupt_dispatch(adev, &ih_data);
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return 0;
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}
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int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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int r, i;
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r = amdgpu_ras_block_late_init(adev, ras_block);
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if (r)
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return r;
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if (amdgpu_ras_is_supported(adev, ras_block->block)) {
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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if (adev->jpeg.harvest_config & (1 << i) ||
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!adev->jpeg.inst[i].ras_poison_irq.funcs)
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continue;
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r = amdgpu_irq_get(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
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if (r)
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goto late_fini;
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}
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}
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return 0;
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late_fini:
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amdgpu_ras_block_late_fini(adev, ras_block);
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return r;
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}
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int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
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{
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int err;
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struct amdgpu_jpeg_ras *ras;
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if (!adev->jpeg.ras)
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return 0;
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ras = adev->jpeg.ras;
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err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
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if (err) {
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dev_err(adev->dev, "Failed to register jpeg ras block!\n");
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return err;
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}
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strcpy(ras->ras_block.ras_comm.name, "jpeg");
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ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
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ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
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adev->jpeg.ras_if = &ras->ras_block.ras_comm;
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if (!ras->ras_block.ras_late_init)
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ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init;
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return 0;
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}
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int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
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enum AMDGPU_UCODE_ID ucode_id)
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{
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struct amdgpu_firmware_info ucode = {
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.ucode_id = AMDGPU_UCODE_ID_JPEG_RAM,
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.mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr,
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.ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr -
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(uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr),
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};
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return psp_execute_ip_fw_load(&adev->psp, &ucode);
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}
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