123 lines
4.2 KiB
C
123 lines
4.2 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_JPEG_H__
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#define __AMDGPU_JPEG_H__
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#include "amdgpu_ras.h"
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#define AMDGPU_MAX_JPEG_INSTANCES 4
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#define AMDGPU_MAX_JPEG_RINGS 8
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#define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)
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#define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1)
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#define WREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \
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do { \
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if (!indirect) { \
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WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
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mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15( \
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JPEG, GET_INST(JPEG, inst_idx), \
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mmUVD_DPG_LMA_CTL, \
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(UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
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offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT | \
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indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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} else { \
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*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
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offset; \
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*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
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value; \
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} \
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} while (0)
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#define RREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, mask_en) \
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({ \
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WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL, \
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(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
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mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
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offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \
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})
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struct amdgpu_jpeg_reg{
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unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];
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};
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struct amdgpu_jpeg_inst {
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struct amdgpu_ring ring_dec[AMDGPU_MAX_JPEG_RINGS];
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struct amdgpu_irq_src irq;
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struct amdgpu_irq_src ras_poison_irq;
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struct amdgpu_jpeg_reg external;
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struct amdgpu_bo *dpg_sram_bo;
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struct dpg_pause_state pause_state;
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void *dpg_sram_cpu_addr;
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uint64_t dpg_sram_gpu_addr;
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uint32_t *dpg_sram_curr_addr;
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uint8_t aid_id;
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};
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struct amdgpu_jpeg_ras {
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struct amdgpu_ras_block_object ras_block;
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};
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struct amdgpu_jpeg {
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uint8_t num_jpeg_inst;
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struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
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unsigned num_jpeg_rings;
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struct amdgpu_jpeg_reg internal;
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unsigned harvest_config;
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struct delayed_work idle_work;
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enum amd_powergating_state cur_state;
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struct mutex jpeg_pg_lock;
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atomic_t total_submission_cnt;
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struct ras_common_if *ras_if;
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struct amdgpu_jpeg_ras *ras;
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uint16_t inst_mask;
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uint8_t num_inst_per_aid;
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bool indirect_sram;
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};
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int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
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int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev);
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int amdgpu_jpeg_suspend(struct amdgpu_device *adev);
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int amdgpu_jpeg_resume(struct amdgpu_device *adev);
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void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring);
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void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring);
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int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry);
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int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev,
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struct ras_common_if *ras_block);
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int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);
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int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
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enum AMDGPU_UCODE_ID ucode_id);
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#endif /*__AMDGPU_JPEG_H__*/
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