67 lines
3.2 KiB
C
67 lines
3.2 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __JPEG_V4_0_3_H__
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#define __JPEG_V4_0_3_H__
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#define regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
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#define regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x404d
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#define regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x404e
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#define regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x404f
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#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ab
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#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ac
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#define regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40a4
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#define regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40a6
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#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40b6
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#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40b7
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#define regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082
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#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x42d4
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#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x42d5
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#define regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085
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#define regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084
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#define regUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089
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#define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x4043
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#define regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET 0x4094
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#define regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET 0x1bffe
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#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
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extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block;
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void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,
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struct amdgpu_job *job,
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struct amdgpu_ib *ib,
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uint32_t flags);
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void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
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unsigned int flags);
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void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned int vmid, uint64_t pd_addr);
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void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);
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void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring);
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void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring);
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void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
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void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask);
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#endif /* __JPEG_V4_0_3_H__ */
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