122 lines
4.5 KiB
C
122 lines
4.5 KiB
C
/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/delay.h>
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#include "amdgpu.h"
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#include "lsdma_v7_0.h"
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#include "amdgpu_lsdma.h"
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#include "lsdma/lsdma_7_0_0_offset.h"
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#include "lsdma/lsdma_7_0_0_sh_mask.h"
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static int lsdma_v7_0_wait_pio_status(struct amdgpu_device *adev)
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{
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return amdgpu_lsdma_wait_for(adev, SOC15_REG_OFFSET(LSDMA, 0, regLSDMA_PIO_STATUS),
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LSDMA_PIO_STATUS__PIO_IDLE_MASK | LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK,
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LSDMA_PIO_STATUS__PIO_IDLE_MASK | LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK);
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}
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static int lsdma_v7_0_copy_mem(struct amdgpu_device *adev,
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uint64_t src_addr,
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uint64_t dst_addr,
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uint64_t size)
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{
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int ret;
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uint32_t tmp;
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr));
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr));
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr));
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr));
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0);
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tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0);
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp);
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ret = lsdma_v7_0_wait_pio_status(adev);
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if (ret)
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dev_err(adev->dev, "LSDMA PIO failed to copy memory!\n");
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return ret;
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}
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static int lsdma_v7_0_fill_mem(struct amdgpu_device *adev,
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uint64_t dst_addr,
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uint32_t data,
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uint64_t size)
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{
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int ret;
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uint32_t tmp;
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONSTFILL_DATA, data);
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr));
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr));
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0);
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tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);
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tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1);
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WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp);
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ret = lsdma_v7_0_wait_pio_status(adev);
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if (ret)
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dev_err(adev->dev, "LSDMA PIO failed to fill memory!\n");
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return ret;
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}
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static void lsdma_v7_0_update_memory_power_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t tmp;
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tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL);
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tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, 0);
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WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
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tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);
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WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
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}
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const struct amdgpu_lsdma_funcs lsdma_v7_0_funcs = {
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.copy_mem = lsdma_v7_0_copy_mem,
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.fill_mem = lsdma_v7_0_fill_mem,
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.update_memory_power_gating = lsdma_v7_0_update_memory_power_gating
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};
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