511 lines
15 KiB
C
511 lines
15 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "core_types.h"
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#include "clk_mgr_internal.h"
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#include "reg_helper.h"
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#include "dm_helpers.h"
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#include "dcn35_smu.h"
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#include "mp/mp_14_0_0_offset.h"
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#include "mp/mp_14_0_0_sh_mask.h"
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/* TODO: Use the real headers when they're correct */
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#define MP1_BASE__INST0_SEG0 0x00016000
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#define MP1_BASE__INST0_SEG1 0x0243FC00
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#define MP1_BASE__INST0_SEG2 0x00DC0000
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#define MP1_BASE__INST0_SEG3 0x00E00000
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#define MP1_BASE__INST0_SEG4 0x00E40000
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#define MP1_BASE__INST0_SEG5 0
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#ifdef BASE_INNER
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#undef BASE_INNER
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#endif
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#define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg
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#define BASE(seg) BASE_INNER(seg)
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#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
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#define FN(reg_name, field) \
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FD(reg_name##__##field)
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#include "logger_types.h"
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#undef DC_LOGGER
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#define DC_LOGGER \
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CTX->logger
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#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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#define VBIOSSMC_MSG_TestMessage 0x1
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#define VBIOSSMC_MSG_GetSmuVersion 0x2
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#define VBIOSSMC_MSG_PowerUpGfx 0x3
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#define VBIOSSMC_MSG_SetDispclkFreq 0x4
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#define VBIOSSMC_MSG_SetDprefclkFreq 0x5 //Not used. DPRef is constant
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#define VBIOSSMC_MSG_SetDppclkFreq 0x6
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#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x7
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#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x8
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#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x9 //Keep it in case VMIN dees not support phy clk
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#define VBIOSSMC_MSG_GetFclkFrequency 0xA
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#define VBIOSSMC_MSG_SetDisplayCount 0xB //Not used anymore
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#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xC //To ask PMFW turn off TMDP 48MHz refclk during display off to save power
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#define VBIOSSMC_MSG_UpdatePmeRestore 0xD
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#define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0xE //Used for WM table txfr
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#define VBIOSSMC_MSG_SetVbiosDramAddrLow 0xF
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#define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10
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#define VBIOSSMC_MSG_TransferTableDram2Smu 0x11
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#define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12
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#define VBIOSSMC_MSG_GetDprefclkFreq 0x13
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#define VBIOSSMC_MSG_GetDtbclkFreq 0x14
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#define VBIOSSMC_MSG_AllowZstatesEntry 0x15
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#define VBIOSSMC_MSG_DisallowZstatesEntry 0x16
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#define VBIOSSMC_MSG_SetDtbClk 0x17
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#define VBIOSSMC_MSG_DispPsrEntry 0x18 ///< Display PSR entry, DMU
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#define VBIOSSMC_MSG_DispPsrExit 0x19 ///< Display PSR exit, DMU
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#define VBIOSSMC_MSG_DisableLSdma 0x1A ///< Disable LSDMA; only sent by VBIOS
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#define VBIOSSMC_MSG_DpControllerPhyStatus 0x1B ///< Inform PMFW about the pre conditions for turning SLDO2 on/off . bit[0]==1 precondition is met, bit[1-2] are for DPPHY number
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#define VBIOSSMC_MSG_QueryIPS2Support 0x1C ///< Return 1: support; else not supported
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#define VBIOSSMC_Message_Count 0x1D
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#define VBIOSSMC_Status_BUSY 0x0
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#define VBIOSSMC_Result_OK 0x1
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#define VBIOSSMC_Result_Failed 0xFF
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#define VBIOSSMC_Result_UnknownCmd 0xFE
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#define VBIOSSMC_Result_CmdRejectedPrereq 0xFD
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#define VBIOSSMC_Result_CmdRejectedBusy 0xFC
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/*
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* Function to be used instead of REG_WAIT macro because the wait ends when
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* the register is NOT EQUAL to zero, and because `the translation in msg_if.h
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* won't work with REG_WAIT.
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*/
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static uint32_t dcn35_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
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{
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uint32_t res_val = VBIOSSMC_Status_BUSY;
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do {
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res_val = REG_READ(MP1_SMN_C2PMSG_91);
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if (res_val != VBIOSSMC_Status_BUSY)
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break;
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if (delay_us >= 1000)
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msleep(delay_us/1000);
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else if (delay_us > 0)
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udelay(delay_us);
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if (clk_mgr->base.ctx->dc->debug.disable_timeout)
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max_retries++;
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} while (max_retries--);
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return res_val;
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}
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static int dcn35_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
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unsigned int msg_id,
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unsigned int param)
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{
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uint32_t result;
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result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
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ASSERT(result == VBIOSSMC_Result_OK);
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if (result != VBIOSSMC_Result_OK) {
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DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id);
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if (result == VBIOSSMC_Status_BUSY)
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return -1;
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}
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/* First clear response register */
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REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
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/* Set the parameter register for the SMU message, unit is Mhz */
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REG_WRITE(MP1_SMN_C2PMSG_83, param);
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/* Trigger the message transaction by writing the message ID */
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REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
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result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
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if (result == VBIOSSMC_Result_Failed) {
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if (msg_id == VBIOSSMC_MSG_TransferTableDram2Smu &&
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param == TABLE_WATERMARKS)
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DC_LOG_WARNING("Watermarks table not configured properly by SMU");
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else
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ASSERT(0);
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REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
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DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id);
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return -1;
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}
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if (IS_SMU_TIMEOUT(result)) {
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ASSERT(0);
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result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
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//dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
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DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id);
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}
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return REG_READ(MP1_SMN_C2PMSG_83);
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}
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int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
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{
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return dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_GetSmuVersion,
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0);
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}
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int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
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{
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int actual_dispclk_set_mhz = -1;
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if (!clk_mgr->smu_present)
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return requested_dispclk_khz;
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/* Unit of SMU msg parameter is Mhz */
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actual_dispclk_set_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDispclkFreq,
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khz_to_mhz_ceil(requested_dispclk_khz));
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smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", requested_dispclk_khz, actual_dispclk_set_mhz);
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return actual_dispclk_set_mhz * 1000;
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}
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int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
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{
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int actual_dprefclk_set_mhz = -1;
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if (!clk_mgr->smu_present)
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return clk_mgr->base.dprefclk_khz;
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actual_dprefclk_set_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDprefclkFreq,
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khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));
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/* TODO: add code for programing DP DTO, currently this is down by command table */
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return actual_dprefclk_set_mhz * 1000;
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}
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int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
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{
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int actual_dcfclk_set_mhz = -1;
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if (!clk_mgr->smu_present)
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return requested_dcfclk_khz;
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actual_dcfclk_set_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
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khz_to_mhz_ceil(requested_dcfclk_khz));
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smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", requested_dcfclk_khz, actual_dcfclk_set_mhz);
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return actual_dcfclk_set_mhz * 1000;
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}
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int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
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{
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int actual_min_ds_dcfclk_mhz = -1;
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if (!clk_mgr->smu_present)
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return requested_min_ds_dcfclk_khz;
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actual_min_ds_dcfclk_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
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khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));
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smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz);
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return actual_min_ds_dcfclk_mhz * 1000;
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}
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int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
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{
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int actual_dppclk_set_mhz = -1;
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if (!clk_mgr->smu_present)
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return requested_dpp_khz;
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actual_dppclk_set_mhz = dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDppclkFreq,
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khz_to_mhz_ceil(requested_dpp_khz));
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smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", requested_dpp_khz, actual_dppclk_set_mhz);
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return actual_dppclk_set_mhz * 1000;
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}
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void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
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{
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if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
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return;
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if (!clk_mgr->smu_present)
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return;
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//TODO: Work with smu team to define optimization options.
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dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDisplayIdleOptimizations,
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idle_info);
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smu_print("%s: VBIOSSMC_MSG_SetDisplayIdleOptimizations idle_info = %x\n", __func__, idle_info);
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}
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void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
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{
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union display_idle_optimization_u idle_info = { 0 };
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if (!clk_mgr->smu_present)
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return;
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if (enable) {
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idle_info.idle_info.df_request_disabled = 1;
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idle_info.idle_info.phy_ref_clk_off = 1;
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}
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dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_SetDisplayIdleOptimizations,
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idle_info.data);
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smu_print("%s smu_enable_phy_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0);
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}
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void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
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{
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if (!clk_mgr->smu_present)
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return;
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dcn35_smu_send_msg_with_param(
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clk_mgr,
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VBIOSSMC_MSG_UpdatePmeRestore,
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0);
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smu_print("%s: SMC_MSG_UpdatePmeRestore\n", __func__);
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}
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void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
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{
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if (!clk_mgr->smu_present)
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return;
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dcn35_smu_send_msg_with_param(clk_mgr,
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VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
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}
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void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
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{
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if (!clk_mgr->smu_present)
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return;
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dcn35_smu_send_msg_with_param(clk_mgr,
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VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
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}
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void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
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{
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if (!clk_mgr->smu_present)
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return;
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dcn35_smu_send_msg_with_param(clk_mgr,
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VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
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}
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void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
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{
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if (!clk_mgr->smu_present)
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return;
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dcn35_smu_send_msg_with_param(clk_mgr,
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VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
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}
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void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)
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{
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unsigned int msg_id, param, retv;
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if (!clk_mgr->smu_present)
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return;
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switch (support) {
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case DCN_ZSTATE_SUPPORT_ALLOW:
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msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
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param = (1 << 10) | (1 << 9) | (1 << 8);
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smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param = 0x%x\n", __func__, param);
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break;
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case DCN_ZSTATE_SUPPORT_DISALLOW:
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msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
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param = 0;
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smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW, param = 0x%x\n", __func__, param);
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break;
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case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY:
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msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
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param = (1 << 10);
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smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z10_ONLY, param = 0x%x\n", __func__, param);
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break;
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case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY:
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msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
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param = (1 << 10) | (1 << 8);
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smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_Z10_ONLY, param = 0x%x\n", __func__, param);
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break;
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case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY:
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msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
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param = (1 << 8);
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smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY, param = 0x%x\n", __func__, param);
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break;
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default: //DCN_ZSTATE_SUPPORT_UNKNOWN
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msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
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param = 0;
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break;
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}
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retv = dcn35_smu_send_msg_with_param(
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clk_mgr,
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msg_id,
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param);
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smu_print("%s: msg_id = %d, param = 0x%x, return = 0x%x\n", __func__, msg_id, param, retv);
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}
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int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)
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{
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int dprefclk;
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if (!clk_mgr->smu_present)
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return 0;
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dprefclk = dcn35_smu_send_msg_with_param(clk_mgr,
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VBIOSSMC_MSG_GetDprefclkFreq,
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0);
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smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk);
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return dprefclk * 1000;
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}
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int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
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{
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int dtbclk;
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if (!clk_mgr->smu_present)
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return 0;
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dtbclk = dcn35_smu_send_msg_with_param(clk_mgr,
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VBIOSSMC_MSG_GetDtbclkFreq,
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0);
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smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk);
|
|
return dtbclk * 1000;
|
|
}
|
|
/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
|
|
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
|
|
{
|
|
if (!clk_mgr->smu_present)
|
|
return;
|
|
|
|
dcn35_smu_send_msg_with_param(
|
|
clk_mgr,
|
|
VBIOSSMC_MSG_SetDtbClk,
|
|
enable);
|
|
smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0);
|
|
}
|
|
|
|
void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
|
|
{
|
|
if (!clk_mgr->smu_present)
|
|
return;
|
|
|
|
dcn35_smu_send_msg_with_param(
|
|
clk_mgr,
|
|
VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
|
|
enable);
|
|
smu_print("%s: smu_enable_48mhz_tmdp_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0);
|
|
}
|
|
|
|
int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
|
|
{
|
|
int retv;
|
|
|
|
if (!clk_mgr->smu_present)
|
|
return 0;
|
|
|
|
retv = dcn35_smu_send_msg_with_param(
|
|
clk_mgr,
|
|
VBIOSSMC_MSG_DispPsrExit,
|
|
0);
|
|
smu_print("%s: smu_exit_low_power_state return = %d\n", __func__, retv);
|
|
return retv;
|
|
}
|
|
|
|
int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)
|
|
{
|
|
int retv;
|
|
|
|
if (!clk_mgr->smu_present)
|
|
return 0;
|
|
|
|
retv = dcn35_smu_send_msg_with_param(
|
|
clk_mgr,
|
|
VBIOSSMC_MSG_QueryIPS2Support,
|
|
0);
|
|
|
|
//smu_print("%s: VBIOSSMC_MSG_QueryIPS2Support return = %x\n", __func__, retv);
|
|
return retv;
|
|
}
|
|
|
|
void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)
|
|
{
|
|
if (!clk_mgr->smu_present)
|
|
return;
|
|
|
|
REG_WRITE(MP1_SMN_C2PMSG_71, param);
|
|
//smu_print("%s: write_ips_scratch = %x\n", __func__, param);
|
|
}
|
|
|
|
uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
|
|
{
|
|
uint32_t retv;
|
|
|
|
if (!clk_mgr->smu_present)
|
|
return 0;
|
|
|
|
retv = REG_READ(MP1_SMN_C2PMSG_71);
|
|
//smu_print("%s: dcn35_smu_read_ips_scratch = %x\n", __func__, retv);
|
|
return retv;
|
|
}
|