462 lines
15 KiB
C
462 lines
15 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "core_types.h"
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#include "reg_helper.h"
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#include "dcn30_dpp.h"
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#include "basics/conversion.h"
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#include "dcn30_cm_common.h"
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#define REG(reg)\
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dpp->tf_regs->reg
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#define CTX \
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dpp->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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dpp->tf_shift->field_name, dpp->tf_mask->field_name
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static void dpp3_enable_cm_block(
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struct dpp *dpp_base)
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{
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struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
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unsigned int cm_bypass_mode = 0;
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// debug option: put CM in bypass mode
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if (dpp_base->ctx->dc->debug.cm_in_bypass)
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cm_bypass_mode = 1;
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REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);
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}
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static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base)
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{
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enum dc_lut_mode mode = LUT_BYPASS;
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uint32_t state_mode;
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uint32_t lut_mode;
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struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
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REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &state_mode);
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if (state_mode == 2) {//Programmable RAM LUT
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REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &lut_mode);
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if (lut_mode == 0)
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mode = LUT_RAM_A;
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else
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mode = LUT_RAM_B;
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}
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return mode;
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}
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static void dpp3_program_gammcor_lut(
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struct dpp *dpp_base,
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const struct pwl_result_data *rgb,
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uint32_t num,
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bool is_ram_a)
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{
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uint32_t i;
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struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
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uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
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uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
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uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
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/*fill in the LUT with all base values to be used by pwl module
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* HW auto increments the LUT index: back-to-back write
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*/
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if (is_rgb_equal(rgb, num)) {
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for (i = 0 ; i < num; i++)
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REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);
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REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);
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} else {
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REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
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CM_GAMCOR_LUT_WRITE_COLOR_MASK, 4);
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for (i = 0 ; i < num; i++)
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REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);
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REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);
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REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
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REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
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CM_GAMCOR_LUT_WRITE_COLOR_MASK, 2);
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for (i = 0 ; i < num; i++)
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REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].green_reg);
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REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_green);
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REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
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REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
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CM_GAMCOR_LUT_WRITE_COLOR_MASK, 1);
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for (i = 0 ; i < num; i++)
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REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].blue_reg);
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REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_blue);
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}
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}
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static void dpp3_power_on_gamcor_lut(
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struct dpp *dpp_base,
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bool power_on)
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{
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struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
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if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
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if (power_on) {
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REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 0);
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REG_WAIT(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, 0, 1, 5);
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} else {
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dpp_base->ctx->dc->optimized_required = true;
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dpp_base->deferred_reg_writes.bits.disable_gamcor = true;
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}
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} else
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REG_SET(CM_MEM_PWR_CTRL, 0,
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GAMCOR_MEM_PWR_DIS, power_on == true ? 0:1);
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}
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void dpp3_program_cm_dealpha(
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struct dpp *dpp_base,
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uint32_t enable, uint32_t additive_blending)
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{
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struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
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REG_SET_2(CM_DEALPHA, 0,
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CM_DEALPHA_EN, enable,
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CM_DEALPHA_ABLND, additive_blending);
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}
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void dpp3_program_cm_bias(
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struct dpp *dpp_base,
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struct CM_bias_params *bias_params)
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{
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struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
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REG_SET(CM_BIAS_CR_R, 0, CM_BIAS_CR_R, bias_params->cm_bias_cr_r);
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REG_SET_2(CM_BIAS_Y_G_CB_B, 0,
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CM_BIAS_Y_G, bias_params->cm_bias_y_g,
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CM_BIAS_CB_B, bias_params->cm_bias_cb_b);
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}
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static void dpp3_gamcor_reg_field(
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struct dcn3_dpp *dpp,
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struct dcn3_xfer_func_reg *reg)
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{
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reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;
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reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;
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reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B;
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reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B;
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reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;
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reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;
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reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;
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reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;
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reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;
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reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;
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reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;
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reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;
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reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B;
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reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B;
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reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;
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reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;
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reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;
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reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;
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reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;
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reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;
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reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B;
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reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B;
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reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;
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reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;
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}
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static void dpp3_configure_gamcor_lut(
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struct dpp *dpp_base,
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bool is_ram_a)
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{
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struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
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REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
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CM_GAMCOR_LUT_WRITE_COLOR_MASK, 7);
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REG_UPDATE(CM_GAMCOR_LUT_CONTROL,
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CM_GAMCOR_LUT_HOST_SEL, is_ram_a == true ? 0:1);
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REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);
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}
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bool dpp3_program_gamcor_lut(
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struct dpp *dpp_base, const struct pwl_params *params)
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{
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enum dc_lut_mode current_mode;
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enum dc_lut_mode next_mode;
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struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
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struct dcn3_xfer_func_reg gam_regs;
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dpp3_enable_cm_block(dpp_base);
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if (params == NULL) { //bypass if we have no pwl data
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REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 0);
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if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
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dpp3_power_on_gamcor_lut(dpp_base, false);
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return false;
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}
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dpp3_power_on_gamcor_lut(dpp_base, true);
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REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 2);
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current_mode = dpp30_get_gamcor_current(dpp_base);
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if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
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next_mode = LUT_RAM_B;
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else
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next_mode = LUT_RAM_A;
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dpp3_power_on_gamcor_lut(dpp_base, true);
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dpp3_configure_gamcor_lut(dpp_base, next_mode == LUT_RAM_A);
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if (next_mode == LUT_RAM_B) {
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gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B);
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gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G);
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gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R);
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gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B);
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gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G);
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gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R);
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gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B);
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gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B);
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gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_G);
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gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMB_END_CNTL2_G);
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gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMB_END_CNTL1_R);
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gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMB_END_CNTL2_R);
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gam_regs.region_start = REG(CM_GAMCOR_RAMB_REGION_0_1);
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gam_regs.region_end = REG(CM_GAMCOR_RAMB_REGION_32_33);
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//New registers in DCN3AG/DCN GAMCOR block
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gam_regs.offset_b = REG(CM_GAMCOR_RAMB_OFFSET_B);
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gam_regs.offset_g = REG(CM_GAMCOR_RAMB_OFFSET_G);
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gam_regs.offset_r = REG(CM_GAMCOR_RAMB_OFFSET_R);
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gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_B);
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gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_G);
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gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_R);
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} else {
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gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMA_START_CNTL_B);
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gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMA_START_CNTL_G);
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gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMA_START_CNTL_R);
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gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B);
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gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G);
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gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R);
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gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMA_END_CNTL1_B);
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gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMA_END_CNTL2_B);
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gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMA_END_CNTL1_G);
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gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMA_END_CNTL2_G);
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gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMA_END_CNTL1_R);
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gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMA_END_CNTL2_R);
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gam_regs.region_start = REG(CM_GAMCOR_RAMA_REGION_0_1);
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gam_regs.region_end = REG(CM_GAMCOR_RAMA_REGION_32_33);
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//New registers in DCN3AG/DCN GAMCOR block
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gam_regs.offset_b = REG(CM_GAMCOR_RAMA_OFFSET_B);
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gam_regs.offset_g = REG(CM_GAMCOR_RAMA_OFFSET_G);
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gam_regs.offset_r = REG(CM_GAMCOR_RAMA_OFFSET_R);
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gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_B);
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gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_G);
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gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_R);
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}
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//get register fields
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dpp3_gamcor_reg_field(dpp, &gam_regs);
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//program register set for LUTA/LUTB
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cm_helper_program_gamcor_xfer_func(dpp_base->ctx, params, &gam_regs);
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dpp3_program_gammcor_lut(dpp_base, params->rgb_resulted, params->hw_points_num,
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next_mode == LUT_RAM_A);
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//select Gamma LUT to use for next frame
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REG_UPDATE(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, next_mode == LUT_RAM_A ? 0:1);
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return true;
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}
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void dpp3_set_hdr_multiplier(
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struct dpp *dpp_base,
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uint32_t multiplier)
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{
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struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
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REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier);
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}
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static void program_gamut_remap(
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struct dcn3_dpp *dpp,
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const uint16_t *regval,
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int select)
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{
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uint16_t selection = 0;
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struct color_matrices_reg gam_regs;
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if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
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REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
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CM_GAMUT_REMAP_MODE, 0);
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return;
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}
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switch (select) {
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case GAMUT_REMAP_COEFF:
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selection = 1;
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break;
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/*this corresponds to GAMUT_REMAP coefficients set B
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*we don't have common coefficient sets in dcn3ag/dcn3
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*/
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case GAMUT_REMAP_COMA_COEFF:
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selection = 2;
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break;
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default:
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break;
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}
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gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
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gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
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gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
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gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
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if (select == GAMUT_REMAP_COEFF) {
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gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
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gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
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cm_helper_program_color_matrices(
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dpp->base.ctx,
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regval,
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&gam_regs);
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} else if (select == GAMUT_REMAP_COMA_COEFF) {
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gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
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gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
|
|
|
|
cm_helper_program_color_matrices(
|
|
dpp->base.ctx,
|
|
regval,
|
|
&gam_regs);
|
|
|
|
}
|
|
//select coefficient set to use
|
|
REG_SET(
|
|
CM_GAMUT_REMAP_CONTROL, 0,
|
|
CM_GAMUT_REMAP_MODE, selection);
|
|
}
|
|
|
|
void dpp3_cm_set_gamut_remap(
|
|
struct dpp *dpp_base,
|
|
const struct dpp_grph_csc_adjustment *adjust)
|
|
{
|
|
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
|
|
int i = 0;
|
|
int gamut_mode;
|
|
|
|
if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
|
|
/* Bypass if type is bypass or hw */
|
|
program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);
|
|
else {
|
|
struct fixed31_32 arr_matrix[12];
|
|
uint16_t arr_reg_val[12];
|
|
|
|
for (i = 0; i < 12; i++)
|
|
arr_matrix[i] = adjust->temperature_matrix[i];
|
|
|
|
convert_float_matrix(
|
|
arr_reg_val, arr_matrix, 12);
|
|
|
|
//current coefficient set in use
|
|
REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &gamut_mode);
|
|
|
|
if (gamut_mode == 0)
|
|
gamut_mode = 1; //use coefficient set A
|
|
else if (gamut_mode == 1)
|
|
gamut_mode = 2;
|
|
else
|
|
gamut_mode = 1;
|
|
|
|
//follow dcn2 approach for now - using only coefficient set A
|
|
program_gamut_remap(dpp, arr_reg_val, gamut_mode);
|
|
}
|
|
}
|
|
|
|
static void read_gamut_remap(struct dcn3_dpp *dpp,
|
|
uint16_t *regval,
|
|
int *select)
|
|
{
|
|
struct color_matrices_reg gam_regs;
|
|
uint32_t selection;
|
|
|
|
//current coefficient set in use
|
|
REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &selection);
|
|
|
|
*select = selection;
|
|
|
|
gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
|
|
gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
|
|
gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
|
|
gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
|
|
|
|
if (*select == GAMUT_REMAP_COEFF) {
|
|
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
|
|
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
|
|
|
|
cm_helper_read_color_matrices(dpp->base.ctx,
|
|
regval,
|
|
&gam_regs);
|
|
|
|
} else if (*select == GAMUT_REMAP_COMA_COEFF) {
|
|
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
|
|
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
|
|
|
|
cm_helper_read_color_matrices(dpp->base.ctx,
|
|
regval,
|
|
&gam_regs);
|
|
}
|
|
}
|
|
|
|
void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,
|
|
struct dpp_grph_csc_adjustment *adjust)
|
|
{
|
|
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
|
|
uint16_t arr_reg_val[12];
|
|
int select;
|
|
|
|
read_gamut_remap(dpp, arr_reg_val, &select);
|
|
|
|
if (select == GAMUT_REMAP_BYPASS) {
|
|
adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
|
|
return;
|
|
}
|
|
|
|
adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
|
|
convert_hw_matrix(adjust->temperature_matrix,
|
|
arr_reg_val, ARRAY_SIZE(arr_reg_val));
|
|
}
|