608 lines
16 KiB
C
608 lines
16 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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/* FILE POLICY AND INTENDED USAGE:
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*
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* This file implements generic display communication protocols such as i2c, aux
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* and scdc. The file should not contain any specific applications of these
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* protocols such as display capability query, detection, or handshaking such as
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* link training.
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*/
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#include "link_ddc.h"
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#include "vector.h"
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#include "dce/dce_aux.h"
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#include "dal_asic_id.h"
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#include "link_dpcd.h"
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#include "dm_helpers.h"
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#include "atomfirmware.h"
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#define DC_LOGGER \
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ddc_service->ctx->logger
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#define DC_LOGGER_INIT(logger)
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static const uint8_t DP_VGA_DONGLE_BRANCH_DEV_NAME[] = "DpVga";
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/* DP to Dual link DVI converter */
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static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
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static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
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struct i2c_payloads {
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struct vector payloads;
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};
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struct aux_payloads {
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struct vector payloads;
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};
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static bool i2c_payloads_create(
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struct dc_context *ctx,
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struct i2c_payloads *payloads,
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uint32_t count)
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{
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if (dal_vector_construct(
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&payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
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return true;
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return false;
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}
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static struct i2c_payload *i2c_payloads_get(struct i2c_payloads *p)
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{
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return (struct i2c_payload *)p->payloads.container;
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}
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static uint32_t i2c_payloads_get_count(struct i2c_payloads *p)
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{
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return p->payloads.count;
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}
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static void i2c_payloads_destroy(struct i2c_payloads *p)
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{
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if (!p)
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return;
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dal_vector_destruct(&p->payloads);
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}
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#define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
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static void i2c_payloads_add(
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struct i2c_payloads *payloads,
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uint32_t address,
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uint32_t len,
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uint8_t *data,
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bool write)
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{
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uint32_t payload_size = EDID_SEGMENT_SIZE;
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uint32_t pos;
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for (pos = 0; pos < len; pos += payload_size) {
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struct i2c_payload payload = {
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.write = write,
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.address = address,
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.length = DDC_MIN(payload_size, len - pos),
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.data = data + pos };
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dal_vector_append(&payloads->payloads, &payload);
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}
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}
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static void ddc_service_construct(
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struct ddc_service *ddc_service,
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struct ddc_service_init_data *init_data)
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{
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enum connector_id connector_id =
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dal_graphics_object_id_get_connector_id(init_data->id);
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struct gpio_service *gpio_service = init_data->ctx->gpio_service;
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struct graphics_object_i2c_info i2c_info;
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struct gpio_ddc_hw_info hw_info;
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struct dc_bios *dcb = init_data->ctx->dc_bios;
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ddc_service->link = init_data->link;
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ddc_service->ctx = init_data->ctx;
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if (init_data->is_dpia_link ||
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dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info) != BP_RESULT_OK) {
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ddc_service->ddc_pin = NULL;
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} else {
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DC_LOGGER_INIT(ddc_service->ctx->logger);
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DC_LOG_DC("BIOS object table - i2c_line: %d", i2c_info.i2c_line);
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DC_LOG_DC("BIOS object table - i2c_engine_id: %d", i2c_info.i2c_engine_id);
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hw_info.ddc_channel = i2c_info.i2c_line;
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if (ddc_service->link != NULL)
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hw_info.hw_supported = i2c_info.i2c_hw_assist;
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else
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hw_info.hw_supported = false;
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ddc_service->ddc_pin = dal_gpio_create_ddc(
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gpio_service,
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i2c_info.gpio_info.clk_a_register_index,
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1 << i2c_info.gpio_info.clk_a_shift,
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&hw_info);
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}
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ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
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ddc_service->flags.FORCE_READ_REPEATED_START = false;
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ddc_service->flags.EDID_STRESS_READ = false;
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ddc_service->flags.IS_INTERNAL_DISPLAY =
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connector_id == CONNECTOR_ID_EDP ||
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connector_id == CONNECTOR_ID_LVDS;
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ddc_service->wa.raw = 0;
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}
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struct ddc_service *link_create_ddc_service(
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struct ddc_service_init_data *init_data)
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{
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struct ddc_service *ddc_service;
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ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);
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if (!ddc_service)
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return NULL;
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ddc_service_construct(ddc_service, init_data);
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return ddc_service;
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}
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static void ddc_service_destruct(struct ddc_service *ddc)
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{
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if (ddc->ddc_pin)
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dal_gpio_destroy_ddc(&ddc->ddc_pin);
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}
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void link_destroy_ddc_service(struct ddc_service **ddc)
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{
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if (!ddc || !*ddc) {
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BREAK_TO_DEBUGGER();
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return;
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}
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ddc_service_destruct(*ddc);
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kfree(*ddc);
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*ddc = NULL;
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}
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void set_ddc_transaction_type(
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struct ddc_service *ddc,
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enum ddc_transaction_type type)
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{
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ddc->transaction_type = type;
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}
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bool link_is_in_aux_transaction_mode(struct ddc_service *ddc)
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{
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switch (ddc->transaction_type) {
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case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
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case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
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case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
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return true;
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default:
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break;
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}
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return false;
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}
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void set_dongle_type(struct ddc_service *ddc,
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enum display_dongle_type dongle_type)
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{
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ddc->dongle_type = dongle_type;
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}
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static uint32_t defer_delay_converter_wa(
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struct ddc_service *ddc,
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uint32_t defer_delay)
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{
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struct dc_link *link = ddc->link;
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if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&
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link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
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(link->dpcd_caps.branch_fw_revision[0] < 0x01 ||
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(link->dpcd_caps.branch_fw_revision[0] == 0x01 &&
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link->dpcd_caps.branch_fw_revision[1] < 0x40)) &&
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!memcmp(link->dpcd_caps.branch_dev_name,
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DP_VGA_DONGLE_BRANCH_DEV_NAME,
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sizeof(link->dpcd_caps.branch_dev_name)))
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return defer_delay > DPVGA_DONGLE_AUX_DEFER_WA_DELAY ?
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defer_delay : DPVGA_DONGLE_AUX_DEFER_WA_DELAY;
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if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
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!memcmp(link->dpcd_caps.branch_dev_name,
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DP_DVI_CONVERTER_ID_4,
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sizeof(link->dpcd_caps.branch_dev_name)))
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return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
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defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
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if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 &&
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!memcmp(link->dpcd_caps.branch_dev_name,
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DP_DVI_CONVERTER_ID_5,
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sizeof(link->dpcd_caps.branch_dev_name)))
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return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ?
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I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay;
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return defer_delay;
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}
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#define DP_TRANSLATOR_DELAY 5
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uint32_t link_get_aux_defer_delay(struct ddc_service *ddc)
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{
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uint32_t defer_delay = 0;
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switch (ddc->transaction_type) {
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case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
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if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
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(DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
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(DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
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ddc->dongle_type)) {
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defer_delay = DP_TRANSLATOR_DELAY;
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defer_delay =
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defer_delay_converter_wa(ddc, defer_delay);
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} else /*sink has a delay different from an Active Converter*/
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defer_delay = 0;
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break;
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case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
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defer_delay = DP_TRANSLATOR_DELAY;
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break;
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default:
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break;
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}
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return defer_delay;
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}
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static bool submit_aux_command(struct ddc_service *ddc,
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struct aux_payload *payload)
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{
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uint32_t retrieved = 0;
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bool ret = false;
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if (!ddc)
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return false;
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if (!payload)
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return false;
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do {
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struct aux_payload current_payload;
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bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >=
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payload->length;
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uint32_t payload_length = is_end_of_payload ?
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payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;
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current_payload.address = payload->address;
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current_payload.data = &payload->data[retrieved];
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current_payload.defer_delay = payload->defer_delay;
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current_payload.i2c_over_aux = payload->i2c_over_aux;
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current_payload.length = payload_length;
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/* set mot (middle of transaction) to false if it is the last payload */
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current_payload.mot = is_end_of_payload ? payload->mot:true;
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current_payload.write_status_update = false;
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current_payload.reply = payload->reply;
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current_payload.write = payload->write;
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ret = link_aux_transfer_with_retries_no_mutex(ddc, ¤t_payload);
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retrieved += payload_length;
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} while (retrieved < payload->length && ret == true);
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return ret;
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}
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bool link_query_ddc_data(
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struct ddc_service *ddc,
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uint32_t address,
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uint8_t *write_buf,
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uint32_t write_size,
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uint8_t *read_buf,
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uint32_t read_size)
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{
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bool success = true;
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uint32_t payload_size =
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link_is_in_aux_transaction_mode(ddc) ?
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DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
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uint32_t write_payloads =
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(write_size + payload_size - 1) / payload_size;
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uint32_t read_payloads =
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(read_size + payload_size - 1) / payload_size;
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uint32_t payloads_num = write_payloads + read_payloads;
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if (!payloads_num)
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return false;
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if (link_is_in_aux_transaction_mode(ddc)) {
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struct aux_payload payload;
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payload.i2c_over_aux = true;
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payload.address = address;
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payload.reply = NULL;
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payload.defer_delay = link_get_aux_defer_delay(ddc);
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payload.write_status_update = false;
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if (write_size != 0) {
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payload.write = true;
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/* should not set mot (middle of transaction) to 0
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* if there are pending read payloads
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*/
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payload.mot = !(read_size == 0);
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payload.length = write_size;
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payload.data = write_buf;
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success = submit_aux_command(ddc, &payload);
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}
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if (read_size != 0 && success) {
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payload.write = false;
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/* should set mot (middle of transaction) to 0
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* since it is the last payload to send
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*/
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payload.mot = false;
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payload.length = read_size;
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payload.data = read_buf;
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success = submit_aux_command(ddc, &payload);
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}
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} else {
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struct i2c_command command = {0};
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struct i2c_payloads payloads;
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if (!i2c_payloads_create(ddc->ctx, &payloads, payloads_num))
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return false;
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command.payloads = i2c_payloads_get(&payloads);
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command.number_of_payloads = 0;
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command.engine = DDC_I2C_COMMAND_ENGINE;
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command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;
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i2c_payloads_add(
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&payloads, address, write_size, write_buf, true);
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i2c_payloads_add(
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&payloads, address, read_size, read_buf, false);
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command.number_of_payloads =
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i2c_payloads_get_count(&payloads);
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success = dm_helpers_submit_i2c(
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ddc->ctx,
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ddc->link,
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&command);
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i2c_payloads_destroy(&payloads);
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}
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return success;
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}
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int link_aux_transfer_raw(struct ddc_service *ddc,
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struct aux_payload *payload,
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enum aux_return_code_type *operation_result)
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{
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if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||
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!ddc->ddc_pin) {
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return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
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} else {
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return dce_aux_transfer_raw(ddc, payload, operation_result);
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}
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}
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uint32_t link_get_fixed_vs_pe_retimer_write_address(struct dc_link *link)
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{
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uint32_t vendor_lttpr_write_address = 0xF004F;
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uint8_t offset;
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switch (link->dpcd_caps.lttpr_caps.phy_repeater_cnt) {
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case 0x80: // 1 lttpr repeater
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offset = 1;
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break;
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case 0x40: // 2 lttpr repeaters
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offset = 2;
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break;
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case 0x20: // 3 lttpr repeaters
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offset = 3;
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break;
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case 0x10: // 4 lttpr repeaters
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offset = 4;
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break;
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case 0x08: // 5 lttpr repeaters
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offset = 5;
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break;
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case 0x04: // 6 lttpr repeaters
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offset = 6;
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break;
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case 0x02: // 7 lttpr repeaters
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offset = 7;
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break;
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case 0x01: // 8 lttpr repeaters
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offset = 8;
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break;
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default:
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offset = 0xFF;
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}
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if (offset != 0xFF) {
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vendor_lttpr_write_address +=
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((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
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}
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return vendor_lttpr_write_address;
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}
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uint32_t link_get_fixed_vs_pe_retimer_read_address(struct dc_link *link)
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{
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return link_get_fixed_vs_pe_retimer_write_address(link) + 4;
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}
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bool link_configure_fixed_vs_pe_retimer(struct ddc_service *ddc, const uint8_t *data, uint32_t length)
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{
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struct aux_payload write_payload = {
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.i2c_over_aux = false,
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.write = true,
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.address = link_get_fixed_vs_pe_retimer_write_address(ddc->link),
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.length = length,
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.data = (uint8_t *) data,
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.reply = NULL,
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.mot = I2C_MOT_UNDEF,
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.write_status_update = false,
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.defer_delay = 0,
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};
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return link_aux_transfer_with_retries_no_mutex(ddc,
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&write_payload);
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}
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bool link_query_fixed_vs_pe_retimer(struct ddc_service *ddc, uint8_t *data, uint32_t length)
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{
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struct aux_payload read_payload = {
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.i2c_over_aux = false,
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.write = false,
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.address = link_get_fixed_vs_pe_retimer_read_address(ddc->link),
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.length = length,
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.data = data,
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.reply = NULL,
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.mot = I2C_MOT_UNDEF,
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.write_status_update = false,
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.defer_delay = 0,
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};
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return link_aux_transfer_with_retries_no_mutex(ddc,
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&read_payload);
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}
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|
bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc,
|
|
struct aux_payload *payload)
|
|
{
|
|
return dce_aux_transfer_with_retries(ddc, payload);
|
|
}
|
|
|
|
|
|
bool try_to_configure_aux_timeout(struct ddc_service *ddc,
|
|
uint32_t timeout)
|
|
{
|
|
bool result = false;
|
|
struct ddc *ddc_pin = ddc->ddc_pin;
|
|
|
|
if ((ddc->link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
|
|
!ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&
|
|
ddc->ctx->dce_version == DCN_VERSION_3_1) {
|
|
/* Fixed VS workaround for AUX timeout */
|
|
const uint32_t fixed_vs_address = 0xF004F;
|
|
const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc};
|
|
|
|
core_link_write_dpcd(ddc->link,
|
|
fixed_vs_address,
|
|
fixed_vs_data,
|
|
sizeof(fixed_vs_data));
|
|
|
|
timeout = 3072;
|
|
}
|
|
|
|
/* Do not try to access nonexistent DDC pin. */
|
|
if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)
|
|
return true;
|
|
|
|
if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {
|
|
ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
|
|
result = true;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
struct ddc *get_ddc_pin(struct ddc_service *ddc_service)
|
|
{
|
|
return ddc_service->ddc_pin;
|
|
}
|
|
|
|
void write_scdc_data(struct ddc_service *ddc_service,
|
|
uint32_t pix_clk,
|
|
bool lte_340_scramble)
|
|
{
|
|
bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
|
|
uint8_t slave_address = HDMI_SCDC_ADDRESS;
|
|
uint8_t offset = HDMI_SCDC_SINK_VERSION;
|
|
uint8_t sink_version = 0;
|
|
uint8_t write_buffer[2] = {0};
|
|
/*Lower than 340 Scramble bit from SCDC caps*/
|
|
|
|
if (ddc_service->link->local_sink &&
|
|
ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
|
|
return;
|
|
|
|
link_query_ddc_data(ddc_service, slave_address, &offset,
|
|
sizeof(offset), &sink_version, sizeof(sink_version));
|
|
if (sink_version == 1) {
|
|
/*Source Version = 1*/
|
|
write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
|
|
write_buffer[1] = 1;
|
|
link_query_ddc_data(ddc_service, slave_address,
|
|
write_buffer, sizeof(write_buffer), NULL, 0);
|
|
/*Read Request from SCDC caps*/
|
|
}
|
|
write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
|
|
|
|
if (over_340_mhz) {
|
|
write_buffer[1] = 3;
|
|
} else if (lte_340_scramble) {
|
|
write_buffer[1] = 1;
|
|
} else {
|
|
write_buffer[1] = 0;
|
|
}
|
|
link_query_ddc_data(ddc_service, slave_address, write_buffer,
|
|
sizeof(write_buffer), NULL, 0);
|
|
}
|
|
|
|
void read_scdc_data(struct ddc_service *ddc_service)
|
|
{
|
|
uint8_t slave_address = HDMI_SCDC_ADDRESS;
|
|
uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
|
|
uint8_t tmds_config = 0;
|
|
|
|
if (ddc_service->link->local_sink &&
|
|
ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
|
|
return;
|
|
|
|
link_query_ddc_data(ddc_service, slave_address, &offset,
|
|
sizeof(offset), &tmds_config, sizeof(tmds_config));
|
|
if (tmds_config & 0x1) {
|
|
union hdmi_scdc_status_flags_data status_data = {0};
|
|
uint8_t scramble_status = 0;
|
|
|
|
offset = HDMI_SCDC_SCRAMBLER_STATUS;
|
|
link_query_ddc_data(ddc_service, slave_address,
|
|
&offset, sizeof(offset), &scramble_status,
|
|
sizeof(scramble_status));
|
|
offset = HDMI_SCDC_STATUS_FLAGS;
|
|
link_query_ddc_data(ddc_service, slave_address,
|
|
&offset, sizeof(offset), &status_data.byte,
|
|
sizeof(status_data.byte));
|
|
}
|
|
}
|