1049 lines
32 KiB
C
1049 lines
32 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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/* FILE POLICY AND INTENDED USAGE:
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* This module implements functionality for training DPIA links.
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*/
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#include "link_dp_training_dpia.h"
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#include "dc.h"
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#include "inc/core_status.h"
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#include "dpcd_defs.h"
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#include "link_dp_dpia.h"
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#include "link_hwss.h"
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#include "dm_helpers.h"
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#include "dmub/inc/dmub_cmd.h"
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#include "link_dpcd.h"
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#include "link_dp_phy.h"
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#include "link_dp_training_8b_10b.h"
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#include "link_dp_capability.h"
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#include "dc_dmub_srv.h"
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#define DC_LOGGER \
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link->ctx->logger
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/* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */
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#define DPIA_CLK_SYNC_DELAY 16000
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/* Extend interval between training status checks for manual testing. */
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#define DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US 60000000
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#define TRAINING_AUX_RD_INTERVAL 100 //us
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/* SET_CONFIG message types sent by driver. */
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enum dpia_set_config_type {
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DPIA_SET_CFG_SET_LINK = 0x01,
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DPIA_SET_CFG_SET_PHY_TEST_MODE = 0x05,
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DPIA_SET_CFG_SET_TRAINING = 0x18,
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DPIA_SET_CFG_SET_VSPE = 0x19
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};
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/* Training stages (TS) in SET_CONFIG(SET_TRAINING) message. */
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enum dpia_set_config_ts {
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DPIA_TS_DPRX_DONE = 0x00, /* Done training DPRX. */
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DPIA_TS_TPS1 = 0x01,
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DPIA_TS_TPS2 = 0x02,
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DPIA_TS_TPS3 = 0x03,
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DPIA_TS_TPS4 = 0x07,
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DPIA_TS_UFP_DONE = 0xff /* Done training DPTX-to-DPIA hop. */
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};
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/* SET_CONFIG message data associated with messages sent by driver. */
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union dpia_set_config_data {
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struct {
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uint8_t mode : 1;
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uint8_t reserved : 7;
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} set_link;
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struct {
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uint8_t stage;
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} set_training;
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struct {
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uint8_t swing : 2;
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uint8_t max_swing_reached : 1;
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uint8_t pre_emph : 2;
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uint8_t max_pre_emph_reached : 1;
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uint8_t reserved : 2;
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} set_vspe;
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uint8_t raw;
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};
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/* Configure link as prescribed in link_setting; set LTTPR mode; and
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* Initialize link training settings.
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* Abort link training if sink unplug detected.
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*
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* @param link DPIA link being trained.
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* @param[in] link_setting Lane count, link rate and downspread control.
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* @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis).
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*/
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static enum link_training_result dpia_configure_link(
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struct dc_link *link,
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const struct link_resource *link_res,
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const struct dc_link_settings *link_setting,
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struct link_training_settings *lt_settings)
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{
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enum dc_status status;
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bool fec_enable;
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DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n",
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__func__,
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link->link_id.enum_id - ENUM_ID_1,
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lt_settings->lttpr_mode);
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dp_decide_training_settings(
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link,
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link_setting,
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lt_settings);
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dp_get_lttpr_mode_override(link, <_settings->lttpr_mode);
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status = dpcd_configure_channel_coding(link, lt_settings);
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if (status != DC_OK && link->is_hpd_pending)
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return LINK_TRAINING_ABORT;
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/* Configure lttpr mode */
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status = dpcd_configure_lttpr_mode(link, lt_settings);
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if (status != DC_OK && link->is_hpd_pending)
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return LINK_TRAINING_ABORT;
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/* Set link rate, lane count and spread. */
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status = dpcd_set_link_settings(link, lt_settings);
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if (status != DC_OK && link->is_hpd_pending)
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return LINK_TRAINING_ABORT;
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if (link->preferred_training_settings.fec_enable != NULL)
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fec_enable = *link->preferred_training_settings.fec_enable;
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else
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fec_enable = true;
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status = dp_set_fec_ready(link, link_res, fec_enable);
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if (status != DC_OK && link->is_hpd_pending)
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return LINK_TRAINING_ABORT;
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return LINK_TRAINING_SUCCESS;
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}
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static enum dc_status core_link_send_set_config(
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struct dc_link *link,
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uint8_t msg_type,
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uint8_t msg_data)
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{
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struct set_config_cmd_payload payload;
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enum set_config_status set_config_result = SET_CONFIG_PENDING;
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/* prepare set_config payload */
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payload.msg_type = msg_type;
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payload.msg_data = msg_data;
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if (!link->ddc->ddc_pin && !link->aux_access_disabled &&
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(dm_helpers_dmub_set_config_sync(link->ctx,
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link, &payload, &set_config_result) == -1)) {
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return DC_ERROR_UNEXPECTED;
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}
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/* set_config should return ACK if successful */
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return (set_config_result == SET_CONFIG_ACK_RECEIVED) ? DC_OK : DC_ERROR_UNEXPECTED;
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}
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/* Build SET_CONFIG message data payload for specified message type. */
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static uint8_t dpia_build_set_config_data(
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enum dpia_set_config_type type,
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struct dc_link *link,
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struct link_training_settings *lt_settings)
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{
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union dpia_set_config_data data;
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data.raw = 0;
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switch (type) {
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case DPIA_SET_CFG_SET_LINK:
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data.set_link.mode = lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT ? 1 : 0;
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break;
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case DPIA_SET_CFG_SET_PHY_TEST_MODE:
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break;
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case DPIA_SET_CFG_SET_VSPE:
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/* Assume all lanes have same drive settings. */
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data.set_vspe.swing = lt_settings->hw_lane_settings[0].VOLTAGE_SWING;
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data.set_vspe.pre_emph = lt_settings->hw_lane_settings[0].PRE_EMPHASIS;
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data.set_vspe.max_swing_reached =
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lt_settings->hw_lane_settings[0].VOLTAGE_SWING == VOLTAGE_SWING_MAX_LEVEL ? 1 : 0;
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data.set_vspe.max_pre_emph_reached =
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lt_settings->hw_lane_settings[0].PRE_EMPHASIS == PRE_EMPHASIS_MAX_LEVEL ? 1 : 0;
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break;
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default:
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ASSERT(false); /* Message type not supported by helper function. */
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break;
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}
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return data.raw;
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}
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/* Convert DC training pattern to DPIA training stage. */
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static enum dc_status convert_trng_ptn_to_trng_stg(enum dc_dp_training_pattern tps, enum dpia_set_config_ts *ts)
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{
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enum dc_status status = DC_OK;
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switch (tps) {
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case DP_TRAINING_PATTERN_SEQUENCE_1:
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*ts = DPIA_TS_TPS1;
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break;
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case DP_TRAINING_PATTERN_SEQUENCE_2:
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*ts = DPIA_TS_TPS2;
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break;
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case DP_TRAINING_PATTERN_SEQUENCE_3:
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*ts = DPIA_TS_TPS3;
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break;
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case DP_TRAINING_PATTERN_SEQUENCE_4:
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*ts = DPIA_TS_TPS4;
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break;
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case DP_TRAINING_PATTERN_VIDEOIDLE:
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*ts = DPIA_TS_DPRX_DONE;
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break;
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default: /* TPS not supported by helper function. */
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ASSERT(false);
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*ts = DPIA_TS_DPRX_DONE;
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status = DC_UNSUPPORTED_VALUE;
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break;
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}
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return status;
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}
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/* Write training pattern to DPCD. */
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static enum dc_status dpcd_set_lt_pattern(
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struct dc_link *link,
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enum dc_dp_training_pattern pattern,
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uint32_t hop)
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{
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union dpcd_training_pattern dpcd_pattern = {0};
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uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
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enum dc_status status;
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if (hop != DPRX)
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dpcd_tps_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
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((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (hop - 1));
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/* DpcdAddress_TrainingPatternSet */
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dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
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dp_training_pattern_to_dpcd_training_pattern(link, pattern);
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dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
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dp_initialize_scrambling_data_symbols(link, pattern);
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if (hop != DPRX) {
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DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
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__func__,
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hop,
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dpcd_tps_offset,
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dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
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} else {
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DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
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__func__,
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dpcd_tps_offset,
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dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
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}
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status = core_link_write_dpcd(
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link,
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dpcd_tps_offset,
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&dpcd_pattern.raw,
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sizeof(dpcd_pattern.raw));
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return status;
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}
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/* Execute clock recovery phase of link training for specified hop in display
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* path.in non-transparent mode:
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* - Driver issues both DPCD and SET_CONFIG transactions.
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* - TPS1 is transmitted for any hops downstream of DPOA.
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* - Drive (VS/PE) only transmitted for the hop immediately downstream of DPOA.
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* - CR for the first hop (DPTX-to-DPIA) is assumed to be successful.
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*
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* @param link DPIA link being trained.
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* @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
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* @param hop Hop in display path. DPRX = 0.
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*/
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static enum link_training_result dpia_training_cr_non_transparent(
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struct dc_link *link,
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const struct link_resource *link_res,
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struct link_training_settings *lt_settings,
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uint32_t hop)
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{
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enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
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uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */
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enum dc_status status;
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uint32_t retries_cr = 0; /* Number of consecutive attempts with same VS or PE. */
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uint32_t retry_count = 0;
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uint32_t wait_time_microsec = TRAINING_AUX_RD_INTERVAL; /* From DP spec, CR read interval is always 100us. */
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enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
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union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
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union lane_align_status_updated dpcd_lane_status_updated = {0};
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union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
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uint8_t set_cfg_data;
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enum dpia_set_config_ts ts;
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repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
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/* Cap of LINK_TRAINING_MAX_CR_RETRY attempts at clock recovery.
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* Fix inherited from perform_clock_recovery_sequence() -
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* the DP equivalent of this function:
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* Required for Synaptics MST hub which can put the LT in
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* infinite loop by switching the VS between level 0 and level 1
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* continuously.
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*/
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while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
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(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
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/* DPTX-to-DPIA */
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if (hop == repeater_cnt) {
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/* Send SET_CONFIG(SET_LINK:LC,LR,LTTPR) to notify DPOA that
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* non-transparent link training has started.
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* This also enables the transmission of clk_sync packets.
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*/
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set_cfg_data = dpia_build_set_config_data(
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DPIA_SET_CFG_SET_LINK,
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link,
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lt_settings);
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status = core_link_send_set_config(
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link,
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DPIA_SET_CFG_SET_LINK,
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set_cfg_data);
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/* CR for this hop is considered successful as long as
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* SET_CONFIG message is acknowledged by DPOA.
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*/
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if (status == DC_OK)
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result = LINK_TRAINING_SUCCESS;
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else
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result = LINK_TRAINING_ABORT;
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break;
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}
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/* DPOA-to-x */
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/* Instruct DPOA to transmit TPS1 then update DPCD. */
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if (retry_count == 0) {
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status = convert_trng_ptn_to_trng_stg(lt_settings->pattern_for_cr, &ts);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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status = core_link_send_set_config(
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link,
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DPIA_SET_CFG_SET_TRAINING,
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ts);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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status = dpcd_set_lt_pattern(link, lt_settings->pattern_for_cr, hop);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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}
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/* Update DPOA drive settings then DPCD. DPOA does only adjusts
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* drive settings for hops immediately downstream.
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*/
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if (hop == repeater_cnt - 1) {
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set_cfg_data = dpia_build_set_config_data(
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DPIA_SET_CFG_SET_VSPE,
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link,
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lt_settings);
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status = core_link_send_set_config(
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link,
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DPIA_SET_CFG_SET_VSPE,
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set_cfg_data);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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}
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status = dpcd_set_lane_settings(link, lt_settings, hop);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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dp_wait_for_training_aux_rd_interval(link, wait_time_microsec);
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/* Read status and adjustment requests from DPCD. */
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status = dp_get_lane_status_and_lane_adjust(
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link,
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lt_settings,
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dpcd_lane_status,
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&dpcd_lane_status_updated,
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dpcd_lane_adjust,
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hop);
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if (status != DC_OK) {
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result = LINK_TRAINING_ABORT;
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break;
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}
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/* Check if clock recovery successful. */
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if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
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DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__);
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result = LINK_TRAINING_SUCCESS;
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break;
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}
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result = dp_get_cr_failure(lane_count, dpcd_lane_status);
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if (dp_is_max_vs_reached(lt_settings))
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break;
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/* Count number of attempts with same drive settings.
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* Note: settings are the same for all lanes,
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* so comparing first lane is sufficient.
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*/
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if ((lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==
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dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)
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&& (lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET ==
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dpcd_lane_adjust[0].bits.PRE_EMPHASIS_LANE))
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retries_cr++;
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else
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retries_cr = 0;
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/* Update VS/PE. */
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dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
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lt_settings->hw_lane_settings,
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lt_settings->dpcd_lane_settings);
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retry_count++;
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}
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/* Abort link training if clock recovery failed due to HPD unplug. */
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if (link->is_hpd_pending)
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result = LINK_TRAINING_ABORT;
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DC_LOG_HW_LINK_TRAINING(
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"%s\n DPIA(%d) clock recovery\n -hop(%d)\n - result(%d)\n - retries(%d)\n - status(%d)\n",
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__func__,
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link->link_id.enum_id - ENUM_ID_1,
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hop,
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result,
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retry_count,
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status);
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return result;
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}
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/* Execute clock recovery phase of link training in transparent LTTPR mode:
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* - Driver only issues DPCD transactions and leaves USB4 tunneling (SET_CONFIG) messages to DPIA.
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* - Driver writes TPS1 to DPCD to kick off training.
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* - Clock recovery (CR) for link is handled by DPOA, which reports result to DPIA on completion.
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* - DPIA communicates result to driver by updating CR status when driver reads DPCD.
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*
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* @param link DPIA link being trained.
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* @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
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*/
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static enum link_training_result dpia_training_cr_transparent(
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struct dc_link *link,
|
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const struct link_resource *link_res,
|
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struct link_training_settings *lt_settings)
|
|
{
|
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enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
|
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enum dc_status status;
|
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uint32_t retries_cr = 0; /* Number of consecutive attempts with same VS or PE. */
|
|
uint32_t retry_count = 0;
|
|
uint32_t wait_time_microsec = lt_settings->cr_pattern_time;
|
|
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
|
|
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
|
|
union lane_align_status_updated dpcd_lane_status_updated = {0};
|
|
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
|
|
|
|
/* Cap of LINK_TRAINING_MAX_CR_RETRY attempts at clock recovery.
|
|
* Fix inherited from perform_clock_recovery_sequence() -
|
|
* the DP equivalent of this function:
|
|
* Required for Synaptics MST hub which can put the LT in
|
|
* infinite loop by switching the VS between level 0 and level 1
|
|
* continuously.
|
|
*/
|
|
while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
|
|
(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
|
|
|
|
/* Write TPS1 (not VS or PE) to DPCD to start CR phase.
|
|
* DPIA sends SET_CONFIG(SET_LINK) to notify DPOA to
|
|
* start link training.
|
|
*/
|
|
if (retry_count == 0) {
|
|
status = dpcd_set_lt_pattern(link, lt_settings->pattern_for_cr, DPRX);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
}
|
|
|
|
dp_wait_for_training_aux_rd_interval(link, wait_time_microsec);
|
|
|
|
/* Read status and adjustment requests from DPCD. */
|
|
status = dp_get_lane_status_and_lane_adjust(
|
|
link,
|
|
lt_settings,
|
|
dpcd_lane_status,
|
|
&dpcd_lane_status_updated,
|
|
dpcd_lane_adjust,
|
|
DPRX);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
|
|
/* Check if clock recovery successful. */
|
|
if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
|
|
DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__);
|
|
result = LINK_TRAINING_SUCCESS;
|
|
break;
|
|
}
|
|
|
|
result = dp_get_cr_failure(lane_count, dpcd_lane_status);
|
|
|
|
if (dp_is_max_vs_reached(lt_settings))
|
|
break;
|
|
|
|
/* Count number of attempts with same drive settings.
|
|
* Note: settings are the same for all lanes,
|
|
* so comparing first lane is sufficient.
|
|
*/
|
|
if ((lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==
|
|
dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)
|
|
&& (lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET ==
|
|
dpcd_lane_adjust[0].bits.PRE_EMPHASIS_LANE))
|
|
retries_cr++;
|
|
else
|
|
retries_cr = 0;
|
|
|
|
/* Update VS/PE. */
|
|
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
|
|
lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
|
|
retry_count++;
|
|
}
|
|
|
|
/* Abort link training if clock recovery failed due to HPD unplug. */
|
|
if (link->is_hpd_pending)
|
|
result = LINK_TRAINING_ABORT;
|
|
|
|
DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) clock recovery\n -hop(%d)\n - result(%d)\n - retries(%d)\n",
|
|
__func__,
|
|
link->link_id.enum_id - ENUM_ID_1,
|
|
DPRX,
|
|
result,
|
|
retry_count);
|
|
|
|
return result;
|
|
}
|
|
|
|
/* Execute clock recovery phase of link training for specified hop in display
|
|
* path.
|
|
*
|
|
* @param link DPIA link being trained.
|
|
* @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
|
|
* @param hop Hop in display path. DPRX = 0.
|
|
*/
|
|
static enum link_training_result dpia_training_cr_phase(
|
|
struct dc_link *link,
|
|
const struct link_resource *link_res,
|
|
struct link_training_settings *lt_settings,
|
|
uint32_t hop)
|
|
{
|
|
enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
|
|
|
|
if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
|
|
result = dpia_training_cr_non_transparent(link, link_res, lt_settings, hop);
|
|
else
|
|
result = dpia_training_cr_transparent(link, link_res, lt_settings);
|
|
|
|
return result;
|
|
}
|
|
|
|
/* Return status read interval during equalization phase. */
|
|
static uint32_t dpia_get_eq_aux_rd_interval(
|
|
const struct dc_link *link,
|
|
const struct link_training_settings *lt_settings,
|
|
uint32_t hop)
|
|
{
|
|
uint32_t wait_time_microsec;
|
|
|
|
if (hop == DPRX)
|
|
wait_time_microsec = lt_settings->eq_pattern_time;
|
|
else
|
|
wait_time_microsec =
|
|
dp_translate_training_aux_read_interval(
|
|
link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);
|
|
|
|
/* Check debug option for extending aux read interval. */
|
|
if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)
|
|
wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;
|
|
|
|
return wait_time_microsec;
|
|
}
|
|
|
|
/* Execute equalization phase of link training for specified hop in display
|
|
* path in non-transparent mode:
|
|
* - driver issues both DPCD and SET_CONFIG transactions.
|
|
* - TPSx is transmitted for any hops downstream of DPOA.
|
|
* - Drive (VS/PE) only transmitted for the hop immediately downstream of DPOA.
|
|
* - EQ for the first hop (DPTX-to-DPIA) is assumed to be successful.
|
|
* - DPRX EQ only reported successful when both DPRX and DPIA requirements (clk sync packets sent) fulfilled.
|
|
*
|
|
* @param link DPIA link being trained.
|
|
* @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
|
|
* @param hop Hop in display path. DPRX = 0.
|
|
*/
|
|
static enum link_training_result dpia_training_eq_non_transparent(
|
|
struct dc_link *link,
|
|
const struct link_resource *link_res,
|
|
struct link_training_settings *lt_settings,
|
|
uint32_t hop)
|
|
{
|
|
enum link_training_result result = LINK_TRAINING_EQ_FAIL_EQ;
|
|
uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */
|
|
uint32_t retries_eq = 0;
|
|
enum dc_status status;
|
|
enum dc_dp_training_pattern tr_pattern;
|
|
uint32_t wait_time_microsec = 0;
|
|
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
|
|
union lane_align_status_updated dpcd_lane_status_updated = {0};
|
|
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
|
|
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
|
|
uint8_t set_cfg_data;
|
|
enum dpia_set_config_ts ts;
|
|
|
|
/* Training pattern is TPS4 for repeater;
|
|
* TPS2/3/4 for DPRX depending on what it supports.
|
|
*/
|
|
if (hop == DPRX)
|
|
tr_pattern = lt_settings->pattern_for_eq;
|
|
else
|
|
tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
|
|
|
|
repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
|
|
|
|
for (retries_eq = 0; retries_eq < LINK_TRAINING_MAX_RETRY_COUNT; retries_eq++) {
|
|
|
|
/* DPTX-to-DPIA equalization always successful. */
|
|
if (hop == repeater_cnt) {
|
|
result = LINK_TRAINING_SUCCESS;
|
|
break;
|
|
}
|
|
|
|
/* Instruct DPOA to transmit TPSn then update DPCD. */
|
|
if (retries_eq == 0) {
|
|
status = convert_trng_ptn_to_trng_stg(tr_pattern, &ts);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
status = core_link_send_set_config(
|
|
link,
|
|
DPIA_SET_CFG_SET_TRAINING,
|
|
ts);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
status = dpcd_set_lt_pattern(link, tr_pattern, hop);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Update DPOA drive settings then DPCD. DPOA only adjusts
|
|
* drive settings for hop immediately downstream.
|
|
*/
|
|
if (hop == repeater_cnt - 1) {
|
|
set_cfg_data = dpia_build_set_config_data(
|
|
DPIA_SET_CFG_SET_VSPE,
|
|
link,
|
|
lt_settings);
|
|
status = core_link_send_set_config(
|
|
link,
|
|
DPIA_SET_CFG_SET_VSPE,
|
|
set_cfg_data);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
}
|
|
status = dpcd_set_lane_settings(link, lt_settings, hop);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
|
|
/* Extend wait time on second equalisation attempt on final hop to
|
|
* ensure clock sync packets have been sent.
|
|
*/
|
|
if (hop == DPRX && retries_eq == 1)
|
|
wait_time_microsec = max(wait_time_microsec, (uint32_t) DPIA_CLK_SYNC_DELAY);
|
|
else
|
|
wait_time_microsec = dpia_get_eq_aux_rd_interval(link, lt_settings, hop);
|
|
|
|
dp_wait_for_training_aux_rd_interval(link, wait_time_microsec);
|
|
|
|
/* Read status and adjustment requests from DPCD. */
|
|
status = dp_get_lane_status_and_lane_adjust(
|
|
link,
|
|
lt_settings,
|
|
dpcd_lane_status,
|
|
&dpcd_lane_status_updated,
|
|
dpcd_lane_adjust,
|
|
hop);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
|
|
/* CR can still fail during EQ phase. Fail training if CR fails. */
|
|
if (!dp_is_cr_done(lane_count, dpcd_lane_status)) {
|
|
result = LINK_TRAINING_EQ_FAIL_CR;
|
|
break;
|
|
}
|
|
|
|
if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
|
|
dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) &&
|
|
dp_is_interlane_aligned(dpcd_lane_status_updated)) {
|
|
result = LINK_TRAINING_SUCCESS;
|
|
break;
|
|
}
|
|
|
|
/* Update VS/PE. */
|
|
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
|
|
lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
|
|
}
|
|
|
|
/* Abort link training if equalization failed due to HPD unplug. */
|
|
if (link->is_hpd_pending)
|
|
result = LINK_TRAINING_ABORT;
|
|
|
|
DC_LOG_HW_LINK_TRAINING(
|
|
"%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n - retries(%d)\n - status(%d)\n",
|
|
__func__,
|
|
link->link_id.enum_id - ENUM_ID_1,
|
|
hop,
|
|
result,
|
|
retries_eq,
|
|
status);
|
|
|
|
return result;
|
|
}
|
|
|
|
/* Execute equalization phase of link training for specified hop in display
|
|
* path in transparent LTTPR mode:
|
|
* - driver only issues DPCD transactions leaves USB4 tunneling (SET_CONFIG) messages to DPIA.
|
|
* - driver writes TPSx to DPCD to notify DPIA that is in equalization phase.
|
|
* - equalization (EQ) for link is handled by DPOA, which reports result to DPIA on completion.
|
|
* - DPIA communicates result to driver by updating EQ status when driver reads DPCD.
|
|
*
|
|
* @param link DPIA link being trained.
|
|
* @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
|
|
* @param hop Hop in display path. DPRX = 0.
|
|
*/
|
|
static enum link_training_result dpia_training_eq_transparent(
|
|
struct dc_link *link,
|
|
const struct link_resource *link_res,
|
|
struct link_training_settings *lt_settings)
|
|
{
|
|
enum link_training_result result = LINK_TRAINING_EQ_FAIL_EQ;
|
|
uint32_t retries_eq = 0;
|
|
enum dc_status status;
|
|
enum dc_dp_training_pattern tr_pattern = lt_settings->pattern_for_eq;
|
|
uint32_t wait_time_microsec;
|
|
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
|
|
union lane_align_status_updated dpcd_lane_status_updated = {0};
|
|
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
|
|
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
|
|
|
|
wait_time_microsec = dpia_get_eq_aux_rd_interval(link, lt_settings, DPRX);
|
|
|
|
for (retries_eq = 0; retries_eq < LINK_TRAINING_MAX_RETRY_COUNT; retries_eq++) {
|
|
|
|
if (retries_eq == 0) {
|
|
status = dpcd_set_lt_pattern(link, tr_pattern, DPRX);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
}
|
|
|
|
dp_wait_for_training_aux_rd_interval(link, wait_time_microsec);
|
|
|
|
/* Read status and adjustment requests from DPCD. */
|
|
status = dp_get_lane_status_and_lane_adjust(
|
|
link,
|
|
lt_settings,
|
|
dpcd_lane_status,
|
|
&dpcd_lane_status_updated,
|
|
dpcd_lane_adjust,
|
|
DPRX);
|
|
if (status != DC_OK) {
|
|
result = LINK_TRAINING_ABORT;
|
|
break;
|
|
}
|
|
|
|
/* CR can still fail during EQ phase. Fail training if CR fails. */
|
|
if (!dp_is_cr_done(lane_count, dpcd_lane_status)) {
|
|
result = LINK_TRAINING_EQ_FAIL_CR;
|
|
break;
|
|
}
|
|
|
|
if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
|
|
dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status)) {
|
|
/* Take into consideration corner case for DP 1.4a LL Compliance CTS as USB4
|
|
* has to share encoders unlike DP and USBC
|
|
*/
|
|
if (dp_is_interlane_aligned(dpcd_lane_status_updated) || (link->skip_fallback_on_link_loss && retries_eq)) {
|
|
result = LINK_TRAINING_SUCCESS;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Update VS/PE. */
|
|
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
|
|
lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
|
|
}
|
|
|
|
/* Abort link training if equalization failed due to HPD unplug. */
|
|
if (link->is_hpd_pending)
|
|
result = LINK_TRAINING_ABORT;
|
|
|
|
DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n - retries(%d)\n",
|
|
__func__,
|
|
link->link_id.enum_id - ENUM_ID_1,
|
|
DPRX,
|
|
result,
|
|
retries_eq);
|
|
|
|
return result;
|
|
}
|
|
|
|
/* Execute equalization phase of link training for specified hop in display
|
|
* path.
|
|
*
|
|
* @param link DPIA link being trained.
|
|
* @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
|
|
* @param hop Hop in display path. DPRX = 0.
|
|
*/
|
|
static enum link_training_result dpia_training_eq_phase(
|
|
struct dc_link *link,
|
|
const struct link_resource *link_res,
|
|
struct link_training_settings *lt_settings,
|
|
uint32_t hop)
|
|
{
|
|
enum link_training_result result;
|
|
|
|
if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
|
|
result = dpia_training_eq_non_transparent(link, link_res, lt_settings, hop);
|
|
else
|
|
result = dpia_training_eq_transparent(link, link_res, lt_settings);
|
|
|
|
return result;
|
|
}
|
|
|
|
/* End training of specified hop in display path. */
|
|
static enum dc_status dpcd_clear_lt_pattern(
|
|
struct dc_link *link,
|
|
uint32_t hop)
|
|
{
|
|
union dpcd_training_pattern dpcd_pattern = {0};
|
|
uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
|
|
enum dc_status status;
|
|
|
|
if (hop != DPRX)
|
|
dpcd_tps_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
|
|
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (hop - 1));
|
|
|
|
status = core_link_write_dpcd(
|
|
link,
|
|
dpcd_tps_offset,
|
|
&dpcd_pattern.raw,
|
|
sizeof(dpcd_pattern.raw));
|
|
|
|
return status;
|
|
}
|
|
|
|
/* End training of specified hop in display path.
|
|
*
|
|
* In transparent LTTPR mode:
|
|
* - driver clears training pattern for the specified hop in DPCD.
|
|
* In non-transparent LTTPR mode:
|
|
* - in addition to clearing training pattern, driver issues USB4 tunneling
|
|
* (SET_CONFIG) messages to notify DPOA when training is done for first hop
|
|
* (DPTX-to-DPIA) and last hop (DPRX).
|
|
*
|
|
* @param link DPIA link being trained.
|
|
* @param hop Hop in display path. DPRX = 0.
|
|
*/
|
|
static enum link_training_result dpia_training_end(
|
|
struct dc_link *link,
|
|
struct link_training_settings *lt_settings,
|
|
uint32_t hop)
|
|
{
|
|
enum link_training_result result = LINK_TRAINING_SUCCESS;
|
|
uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */
|
|
enum dc_status status;
|
|
|
|
if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
|
|
|
|
repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
|
|
|
|
if (hop == repeater_cnt) { /* DPTX-to-DPIA */
|
|
/* Send SET_CONFIG(SET_TRAINING:0xff) to notify DPOA that
|
|
* DPTX-to-DPIA hop trained. No DPCD write needed for first hop.
|
|
*/
|
|
status = core_link_send_set_config(
|
|
link,
|
|
DPIA_SET_CFG_SET_TRAINING,
|
|
DPIA_TS_UFP_DONE);
|
|
if (status != DC_OK)
|
|
result = LINK_TRAINING_ABORT;
|
|
} else { /* DPOA-to-x */
|
|
/* Write 0x0 to TRAINING_PATTERN_SET */
|
|
status = dpcd_clear_lt_pattern(link, hop);
|
|
if (status != DC_OK)
|
|
result = LINK_TRAINING_ABORT;
|
|
}
|
|
|
|
/* Notify DPOA that non-transparent link training of DPRX done. */
|
|
if (hop == DPRX && result != LINK_TRAINING_ABORT) {
|
|
status = core_link_send_set_config(
|
|
link,
|
|
DPIA_SET_CFG_SET_TRAINING,
|
|
DPIA_TS_DPRX_DONE);
|
|
if (status != DC_OK)
|
|
result = LINK_TRAINING_ABORT;
|
|
}
|
|
|
|
} else { /* non-LTTPR or transparent LTTPR. */
|
|
|
|
/* Write 0x0 to TRAINING_PATTERN_SET */
|
|
status = dpcd_clear_lt_pattern(link, hop);
|
|
if (status != DC_OK)
|
|
result = LINK_TRAINING_ABORT;
|
|
|
|
}
|
|
|
|
DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) end\n - hop(%d)\n - result(%d)\n - LTTPR mode(%d)\n",
|
|
__func__,
|
|
link->link_id.enum_id - ENUM_ID_1,
|
|
hop,
|
|
result,
|
|
lt_settings->lttpr_mode);
|
|
|
|
return result;
|
|
}
|
|
|
|
/* When aborting training of specified hop in display path, clean up by:
|
|
* - Attempting to clear DPCD TRAINING_PATTERN_SET, LINK_BW_SET and LANE_COUNT_SET.
|
|
* - Sending SET_CONFIG(SET_LINK) with lane count and link rate set to 0.
|
|
*
|
|
* @param link DPIA link being trained.
|
|
* @param hop Hop in display path. DPRX = 0.
|
|
*/
|
|
static void dpia_training_abort(
|
|
struct dc_link *link,
|
|
struct link_training_settings *lt_settings,
|
|
uint32_t hop)
|
|
{
|
|
uint8_t data = 0;
|
|
uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
|
|
|
|
DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) aborting\n - LTTPR mode(%d)\n - HPD(%d)\n",
|
|
__func__,
|
|
link->link_id.enum_id - ENUM_ID_1,
|
|
lt_settings->lttpr_mode,
|
|
link->is_hpd_pending);
|
|
|
|
/* Abandon clean-up if sink unplugged. */
|
|
if (link->is_hpd_pending)
|
|
return;
|
|
|
|
if (hop != DPRX)
|
|
dpcd_tps_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
|
|
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (hop - 1));
|
|
|
|
core_link_write_dpcd(link, dpcd_tps_offset, &data, 1);
|
|
core_link_write_dpcd(link, DP_LINK_BW_SET, &data, 1);
|
|
core_link_write_dpcd(link, DP_LANE_COUNT_SET, &data, 1);
|
|
core_link_send_set_config(link, DPIA_SET_CFG_SET_LINK, data);
|
|
}
|
|
|
|
enum link_training_result dpia_perform_link_training(
|
|
struct dc_link *link,
|
|
const struct link_resource *link_res,
|
|
const struct dc_link_settings *link_setting,
|
|
bool skip_video_pattern)
|
|
{
|
|
enum link_training_result result;
|
|
struct link_training_settings lt_settings = {0};
|
|
uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */
|
|
int8_t repeater_id; /* Current hop. */
|
|
|
|
struct dc_link_settings link_settings = *link_setting; // non-const copy to pass in
|
|
|
|
lt_settings.lttpr_mode = dp_decide_lttpr_mode(link, &link_settings);
|
|
|
|
/* Configure link as prescribed in link_setting and set LTTPR mode. */
|
|
result = dpia_configure_link(link, link_res, link_setting, <_settings);
|
|
if (result != LINK_TRAINING_SUCCESS)
|
|
return result;
|
|
|
|
if (lt_settings.lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
|
|
repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
|
|
|
|
/* Train each hop in turn starting with the one closest to DPTX.
|
|
* In transparent or non-LTTPR mode, train only the final hop (DPRX).
|
|
*/
|
|
for (repeater_id = repeater_cnt; repeater_id >= 0; repeater_id--) {
|
|
/* Clock recovery. */
|
|
result = dpia_training_cr_phase(link, link_res, <_settings, repeater_id);
|
|
if (result != LINK_TRAINING_SUCCESS)
|
|
break;
|
|
|
|
/* Equalization. */
|
|
result = dpia_training_eq_phase(link, link_res, <_settings, repeater_id);
|
|
if (result != LINK_TRAINING_SUCCESS)
|
|
break;
|
|
|
|
/* Stop training hop. */
|
|
result = dpia_training_end(link, <_settings, repeater_id);
|
|
if (result != LINK_TRAINING_SUCCESS)
|
|
break;
|
|
}
|
|
|
|
/* Double-check link status if training successful; gracefully abort
|
|
* training of current hop if training failed due to message tunneling
|
|
* failure; end training of hop if training ended conventionally and
|
|
* falling back to lower bandwidth settings possible.
|
|
*/
|
|
if (result == LINK_TRAINING_SUCCESS) {
|
|
fsleep(5000);
|
|
if (!link->skip_fallback_on_link_loss)
|
|
result = dp_check_link_loss_status(link, <_settings);
|
|
} else if (result == LINK_TRAINING_ABORT)
|
|
dpia_training_abort(link, <_settings, repeater_id);
|
|
else
|
|
dpia_training_end(link, <_settings, repeater_id);
|
|
|
|
return result;
|
|
}
|