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1af13bc6d0
Add intel_de_read64_2x32() wrapper for the uncore version of the same, and use it to read the high and low frame registers. Avoid duplicating code for existing helpers. The slight functional difference is checking that the entire high register remains the same across two reads, instead of just the part we're interested in. This should be of no consequence. (Unless those bits function as a PRNG.) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/33853549adff82045b95af527e14cfdff5712470.1673873708.git.jani.nikula@intel.com
126 lines
3.3 KiB
C
126 lines
3.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DE_H__
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#define __INTEL_DE_H__
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_uncore.h"
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static inline u32
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intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
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{
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return intel_uncore_read(&i915->uncore, reg);
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}
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static inline u8
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intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg)
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{
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return intel_uncore_read8(&i915->uncore, reg);
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}
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static inline u64
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intel_de_read64_2x32(struct drm_i915_private *i915,
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i915_reg_t lower_reg, i915_reg_t upper_reg)
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{
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return intel_uncore_read64_2x32(&i915->uncore, lower_reg, upper_reg);
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}
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static inline void
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intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
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{
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intel_uncore_posting_read(&i915->uncore, reg);
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}
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static inline void
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intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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intel_uncore_write(&i915->uncore, reg, val);
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}
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static inline u32
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intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
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{
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return intel_uncore_rmw(&i915->uncore, reg, clear, set);
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}
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static inline int
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intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
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}
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static inline int
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intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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return intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout);
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}
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static inline int
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__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms, u32 *out_value)
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{
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return __intel_wait_for_register(&i915->uncore, reg, mask, value,
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fast_timeout_us, slow_timeout_ms, out_value);
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}
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static inline int
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intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
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}
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static inline int
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intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
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}
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/*
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* Unlocked mmio-accessors, think carefully before using these.
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*
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* Certain architectures will die if the same cacheline is concurrently accessed
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* by different clients (e.g. on Ivybridge). Access to registers should
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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static inline u32
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intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
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{
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u32 val;
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val = intel_uncore_read_fw(&i915->uncore, reg);
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trace_i915_reg_rw(false, reg, val, sizeof(val), true);
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return val;
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}
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static inline void
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intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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trace_i915_reg_rw(true, reg, val, sizeof(val), true);
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intel_uncore_write_fw(&i915->uncore, reg, val);
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}
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static inline u32
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intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
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{
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return intel_uncore_read_notrace(&i915->uncore, reg);
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}
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static inline void
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intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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intel_uncore_write_notrace(&i915->uncore, reg, val);
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}
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#endif /* __INTEL_DE_H__ */
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