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![Lukasz Majewski](/assets/img/avatar_default.png)
The commit d0a0ce3e77
("thermal: exynos: Add
missing definations and code cleanup") has removed setting of test MUX address
value at TMU configuration setting.
This field is not present on Exynos4210 and Exynos5 SoCs. However on Exynos4412
SoC it is required to set this field after reset because without it TMU shows
maximal available temperature, which causes immediate platform shutdown.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
766 lines
20 KiB
C
766 lines
20 KiB
C
/*
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* exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
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*
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* Copyright (C) 2011 Samsung Electronics
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* Donggeun Kim <dg77.kim@samsung.com>
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* Amit Daniel Kachhap <amit.kachhap@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include "exynos_thermal_common.h"
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#include "exynos_tmu.h"
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#include "exynos_tmu_data.h"
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/**
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* struct exynos_tmu_data : A structure to hold the private data of the TMU
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driver
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* @id: identifier of the one instance of the TMU controller.
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* @pdata: pointer to the tmu platform/configuration data
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* @base: base address of the single instance of the TMU controller.
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* @base_common: base address of the common registers of the TMU controller.
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* @irq: irq number of the TMU controller.
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* @soc: id of the SOC type.
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* @irq_work: pointer to the irq work structure.
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* @lock: lock to implement synchronization.
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* @clk: pointer to the clock structure.
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* @temp_error1: fused value of the first point trim.
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* @temp_error2: fused value of the second point trim.
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* @regulator: pointer to the TMU regulator structure.
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* @reg_conf: pointer to structure to register with core thermal.
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*/
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struct exynos_tmu_data {
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int id;
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struct exynos_tmu_platform_data *pdata;
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void __iomem *base;
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void __iomem *base_common;
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int irq;
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enum soc_type soc;
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struct work_struct irq_work;
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struct mutex lock;
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struct clk *clk;
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u8 temp_error1, temp_error2;
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struct regulator *regulator;
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struct thermal_sensor_conf *reg_conf;
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};
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/*
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* TMU treats temperature as a mapped temperature code.
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* The temperature is converted differently depending on the calibration type.
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*/
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static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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int temp_code;
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if (pdata->cal_mode == HW_MODE)
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return temp;
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if (data->soc == SOC_ARCH_EXYNOS4210)
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/* temp should range between 25 and 125 */
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if (temp < 25 || temp > 125) {
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temp_code = -EINVAL;
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goto out;
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}
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switch (pdata->cal_type) {
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case TYPE_TWO_POINT_TRIMMING:
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temp_code = (temp - pdata->first_point_trim) *
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(data->temp_error2 - data->temp_error1) /
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(pdata->second_point_trim - pdata->first_point_trim) +
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data->temp_error1;
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break;
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case TYPE_ONE_POINT_TRIMMING:
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temp_code = temp + data->temp_error1 - pdata->first_point_trim;
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break;
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default:
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temp_code = temp + pdata->default_temp_offset;
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break;
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}
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out:
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return temp_code;
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}
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/*
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* Calculate a temperature value from a temperature code.
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* The unit of the temperature is degree Celsius.
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*/
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static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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int temp;
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if (pdata->cal_mode == HW_MODE)
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return temp_code;
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if (data->soc == SOC_ARCH_EXYNOS4210)
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/* temp_code should range between 75 and 175 */
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if (temp_code < 75 || temp_code > 175) {
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temp = -ENODATA;
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goto out;
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}
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switch (pdata->cal_type) {
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case TYPE_TWO_POINT_TRIMMING:
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temp = (temp_code - data->temp_error1) *
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(pdata->second_point_trim - pdata->first_point_trim) /
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(data->temp_error2 - data->temp_error1) +
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pdata->first_point_trim;
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break;
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case TYPE_ONE_POINT_TRIMMING:
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temp = temp_code - data->temp_error1 + pdata->first_point_trim;
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break;
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default:
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temp = temp_code - pdata->default_temp_offset;
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break;
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}
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out:
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return temp;
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}
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static int exynos_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct exynos_tmu_platform_data *pdata = data->pdata;
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const struct exynos_tmu_registers *reg = pdata->registers;
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unsigned int status, trim_info = 0, con;
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unsigned int rising_threshold = 0, falling_threshold = 0;
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int ret = 0, threshold_code, i, trigger_levs = 0;
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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if (TMU_SUPPORTS(pdata, READY_STATUS)) {
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status = readb(data->base + reg->tmu_status);
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if (!status) {
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ret = -EBUSY;
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goto out;
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}
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}
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if (TMU_SUPPORTS(pdata, TRIM_RELOAD))
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__raw_writel(1, data->base + reg->triminfo_ctrl);
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if (pdata->cal_mode == HW_MODE)
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goto skip_calib_data;
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/* Save trimming info in order to perform calibration */
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if (data->soc == SOC_ARCH_EXYNOS5440) {
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/*
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* For exynos5440 soc triminfo value is swapped between TMU0 and
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* TMU2, so the below logic is needed.
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*/
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switch (data->id) {
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case 0:
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trim_info = readl(data->base +
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EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
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break;
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case 1:
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trim_info = readl(data->base + reg->triminfo_data);
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break;
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case 2:
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trim_info = readl(data->base -
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EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
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}
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} else {
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trim_info = readl(data->base + reg->triminfo_data);
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}
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data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
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data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
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EXYNOS_TMU_TEMP_MASK);
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if (!data->temp_error1 ||
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(pdata->min_efuse_value > data->temp_error1) ||
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(data->temp_error1 > pdata->max_efuse_value))
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data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
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if (!data->temp_error2)
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data->temp_error2 =
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(pdata->efuse_value >> reg->triminfo_85_shift) &
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EXYNOS_TMU_TEMP_MASK;
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skip_calib_data:
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if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) {
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dev_err(&pdev->dev, "Invalid max trigger level\n");
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goto out;
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}
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for (i = 0; i < pdata->max_trigger_level; i++) {
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if (!pdata->trigger_levels[i])
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continue;
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if ((pdata->trigger_type[i] == HW_TRIP) &&
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(!pdata->trigger_levels[pdata->max_trigger_level - 1])) {
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dev_err(&pdev->dev, "Invalid hw trigger level\n");
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ret = -EINVAL;
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goto out;
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}
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/* Count trigger levels except the HW trip*/
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if (!(pdata->trigger_type[i] == HW_TRIP))
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trigger_levs++;
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}
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if (data->soc == SOC_ARCH_EXYNOS4210) {
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/* Write temperature code for threshold */
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threshold_code = temp_to_code(data, pdata->threshold);
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if (threshold_code < 0) {
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ret = threshold_code;
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goto out;
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}
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writeb(threshold_code,
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data->base + reg->threshold_temp);
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for (i = 0; i < trigger_levs; i++)
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writeb(pdata->trigger_levels[i], data->base +
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reg->threshold_th0 + i * sizeof(reg->threshold_th0));
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writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
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} else {
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/* Write temperature code for rising and falling threshold */
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for (i = 0;
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i < trigger_levs && i < EXYNOS_MAX_TRIGGER_PER_REG; i++) {
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threshold_code = temp_to_code(data,
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pdata->trigger_levels[i]);
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if (threshold_code < 0) {
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ret = threshold_code;
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goto out;
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}
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rising_threshold |= threshold_code << 8 * i;
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if (pdata->threshold_falling) {
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threshold_code = temp_to_code(data,
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pdata->trigger_levels[i] -
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pdata->threshold_falling);
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if (threshold_code > 0)
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falling_threshold |=
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threshold_code << 8 * i;
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}
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}
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writel(rising_threshold,
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data->base + reg->threshold_th0);
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writel(falling_threshold,
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data->base + reg->threshold_th1);
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writel((reg->inten_rise_mask << reg->inten_rise_shift) |
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(reg->inten_fall_mask << reg->inten_fall_shift),
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data->base + reg->tmu_intclear);
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/* if last threshold limit is also present */
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i = pdata->max_trigger_level - 1;
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if (pdata->trigger_levels[i] &&
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(pdata->trigger_type[i] == HW_TRIP)) {
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threshold_code = temp_to_code(data,
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pdata->trigger_levels[i]);
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if (threshold_code < 0) {
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ret = threshold_code;
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goto out;
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}
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if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) {
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/* 1-4 level to be assigned in th0 reg */
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rising_threshold |= threshold_code << 8 * i;
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writel(rising_threshold,
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data->base + reg->threshold_th0);
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} else if (i == EXYNOS_MAX_TRIGGER_PER_REG) {
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/* 5th level to be assigned in th2 reg */
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rising_threshold =
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threshold_code << reg->threshold_th3_l0_shift;
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writel(rising_threshold,
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data->base + reg->threshold_th2);
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}
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con = readl(data->base + reg->tmu_ctrl);
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con |= (1 << reg->therm_trip_en_shift);
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writel(con, data->base + reg->tmu_ctrl);
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}
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}
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/*Clear the PMIN in the common TMU register*/
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if (reg->tmu_pmin && !data->id)
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writel(0, data->base_common + reg->tmu_pmin);
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out:
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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return ret;
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}
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static void exynos_tmu_control(struct platform_device *pdev, bool on)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct exynos_tmu_platform_data *pdata = data->pdata;
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const struct exynos_tmu_registers *reg = pdata->registers;
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unsigned int con, interrupt_en, cal_val;
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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con = readl(data->base + reg->tmu_ctrl);
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if (pdata->test_mux)
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con |= (pdata->test_mux << reg->test_mux_addr_shift);
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if (pdata->reference_voltage) {
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con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift);
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con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
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}
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if (pdata->gain) {
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con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift);
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con |= (pdata->gain << reg->buf_slope_sel_shift);
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}
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if (pdata->noise_cancel_mode) {
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con &= ~(reg->therm_trip_mode_mask <<
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reg->therm_trip_mode_shift);
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con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);
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}
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if (pdata->cal_mode == HW_MODE) {
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con &= ~(reg->calib_mode_mask << reg->calib_mode_shift);
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cal_val = 0;
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switch (pdata->cal_type) {
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case TYPE_TWO_POINT_TRIMMING:
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cal_val = 3;
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break;
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case TYPE_ONE_POINT_TRIMMING_85:
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cal_val = 2;
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break;
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case TYPE_ONE_POINT_TRIMMING_25:
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cal_val = 1;
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break;
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case TYPE_NONE:
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break;
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default:
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dev_err(&pdev->dev, "Invalid calibration type, using none\n");
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}
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con |= cal_val << reg->calib_mode_shift;
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}
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if (on) {
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con |= (1 << reg->core_en_shift);
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interrupt_en =
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pdata->trigger_enable[3] << reg->inten_rise3_shift |
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pdata->trigger_enable[2] << reg->inten_rise2_shift |
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pdata->trigger_enable[1] << reg->inten_rise1_shift |
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pdata->trigger_enable[0] << reg->inten_rise0_shift;
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if (TMU_SUPPORTS(pdata, FALLING_TRIP))
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interrupt_en |=
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interrupt_en << reg->inten_fall0_shift;
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} else {
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con &= ~(1 << reg->core_en_shift);
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interrupt_en = 0; /* Disable all interrupts */
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}
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writel(interrupt_en, data->base + reg->tmu_inten);
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writel(con, data->base + reg->tmu_ctrl);
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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}
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static int exynos_tmu_read(struct exynos_tmu_data *data)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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const struct exynos_tmu_registers *reg = pdata->registers;
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u8 temp_code;
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int temp;
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|
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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temp_code = readb(data->base + reg->tmu_cur_temp);
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temp = code_to_temp(data, temp_code);
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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return temp;
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}
|
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|
|
#ifdef CONFIG_THERMAL_EMULATION
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static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
|
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{
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struct exynos_tmu_data *data = drv_data;
|
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struct exynos_tmu_platform_data *pdata = data->pdata;
|
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const struct exynos_tmu_registers *reg = pdata->registers;
|
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unsigned int val;
|
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int ret = -EINVAL;
|
|
|
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if (!TMU_SUPPORTS(pdata, EMULATION))
|
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goto out;
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|
|
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if (temp && temp < MCELSIUS)
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goto out;
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|
|
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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|
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val = readl(data->base + reg->emul_con);
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|
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if (temp) {
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temp /= MCELSIUS;
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|
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if (TMU_SUPPORTS(pdata, EMUL_TIME)) {
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val &= ~(EXYNOS_EMUL_TIME_MASK << reg->emul_time_shift);
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val |= (EXYNOS_EMUL_TIME << reg->emul_time_shift);
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}
|
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val &= ~(EXYNOS_EMUL_DATA_MASK << reg->emul_temp_shift);
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val |= (temp_to_code(data, temp) << reg->emul_temp_shift) |
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EXYNOS_EMUL_ENABLE;
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} else {
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val &= ~EXYNOS_EMUL_ENABLE;
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}
|
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|
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writel(val, data->base + reg->emul_con);
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|
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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return 0;
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out:
|
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return ret;
|
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}
|
|
#else
|
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static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
|
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{ return -EINVAL; }
|
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#endif/*CONFIG_THERMAL_EMULATION*/
|
|
|
|
static void exynos_tmu_work(struct work_struct *work)
|
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{
|
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struct exynos_tmu_data *data = container_of(work,
|
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struct exynos_tmu_data, irq_work);
|
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struct exynos_tmu_platform_data *pdata = data->pdata;
|
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const struct exynos_tmu_registers *reg = pdata->registers;
|
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unsigned int val_irq, val_type;
|
|
|
|
/* Find which sensor generated this interrupt */
|
|
if (reg->tmu_irqstatus) {
|
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val_type = readl(data->base_common + reg->tmu_irqstatus);
|
|
if (!((val_type >> data->id) & 0x1))
|
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goto out;
|
|
}
|
|
|
|
exynos_report_trigger(data->reg_conf);
|
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mutex_lock(&data->lock);
|
|
clk_enable(data->clk);
|
|
|
|
/* TODO: take action based on particular interrupt */
|
|
val_irq = readl(data->base + reg->tmu_intstat);
|
|
/* clear the interrupts */
|
|
writel(val_irq, data->base + reg->tmu_intclear);
|
|
|
|
clk_disable(data->clk);
|
|
mutex_unlock(&data->lock);
|
|
out:
|
|
enable_irq(data->irq);
|
|
}
|
|
|
|
static irqreturn_t exynos_tmu_irq(int irq, void *id)
|
|
{
|
|
struct exynos_tmu_data *data = id;
|
|
|
|
disable_irq_nosync(irq);
|
|
schedule_work(&data->irq_work);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct of_device_id exynos_tmu_match[] = {
|
|
{
|
|
.compatible = "samsung,exynos4210-tmu",
|
|
.data = (void *)EXYNOS4210_TMU_DRV_DATA,
|
|
},
|
|
{
|
|
.compatible = "samsung,exynos4412-tmu",
|
|
.data = (void *)EXYNOS4412_TMU_DRV_DATA,
|
|
},
|
|
{
|
|
.compatible = "samsung,exynos5250-tmu",
|
|
.data = (void *)EXYNOS5250_TMU_DRV_DATA,
|
|
},
|
|
{
|
|
.compatible = "samsung,exynos5440-tmu",
|
|
.data = (void *)EXYNOS5440_TMU_DRV_DATA,
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, exynos_tmu_match);
|
|
|
|
static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
|
|
struct platform_device *pdev, int id)
|
|
{
|
|
struct exynos_tmu_init_data *data_table;
|
|
struct exynos_tmu_platform_data *tmu_data;
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
|
|
if (!match)
|
|
return NULL;
|
|
data_table = (struct exynos_tmu_init_data *) match->data;
|
|
if (!data_table || id >= data_table->tmu_count)
|
|
return NULL;
|
|
tmu_data = data_table->tmu_data;
|
|
return (struct exynos_tmu_platform_data *) (tmu_data + id);
|
|
}
|
|
|
|
static int exynos_map_dt_data(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct exynos_tmu_platform_data *pdata;
|
|
struct resource res;
|
|
int ret;
|
|
|
|
if (!data || !pdev->dev.of_node)
|
|
return -ENODEV;
|
|
|
|
/*
|
|
* Try enabling the regulator if found
|
|
* TODO: Add regulator as an SOC feature, so that regulator enable
|
|
* is a compulsory call.
|
|
*/
|
|
data->regulator = devm_regulator_get(&pdev->dev, "vtmu");
|
|
if (!IS_ERR(data->regulator)) {
|
|
ret = regulator_enable(data->regulator);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to enable vtmu\n");
|
|
return ret;
|
|
}
|
|
} else {
|
|
dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
|
|
}
|
|
|
|
data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
|
|
if (data->id < 0)
|
|
data->id = 0;
|
|
|
|
data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
|
|
if (data->irq <= 0) {
|
|
dev_err(&pdev->dev, "failed to get IRQ\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
|
|
dev_err(&pdev->dev, "failed to get Resource 0\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
|
|
if (!data->base) {
|
|
dev_err(&pdev->dev, "Failed to ioremap memory\n");
|
|
return -EADDRNOTAVAIL;
|
|
}
|
|
|
|
pdata = exynos_get_driver_data(pdev, data->id);
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "No platform init data supplied.\n");
|
|
return -ENODEV;
|
|
}
|
|
data->pdata = pdata;
|
|
/*
|
|
* Check if the TMU shares some registers and then try to map the
|
|
* memory of common registers.
|
|
*/
|
|
if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
|
|
return 0;
|
|
|
|
if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
|
|
dev_err(&pdev->dev, "failed to get Resource 1\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
data->base_common = devm_ioremap(&pdev->dev, res.start,
|
|
resource_size(&res));
|
|
if (!data->base_common) {
|
|
dev_err(&pdev->dev, "Failed to ioremap memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_tmu_probe(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data;
|
|
struct exynos_tmu_platform_data *pdata;
|
|
struct thermal_sensor_conf *sensor_conf;
|
|
int ret, i;
|
|
|
|
data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
|
|
GFP_KERNEL);
|
|
if (!data) {
|
|
dev_err(&pdev->dev, "Failed to allocate driver structure\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
mutex_init(&data->lock);
|
|
|
|
ret = exynos_map_dt_data(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pdata = data->pdata;
|
|
|
|
INIT_WORK(&data->irq_work, exynos_tmu_work);
|
|
|
|
data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
|
|
if (IS_ERR(data->clk)) {
|
|
dev_err(&pdev->dev, "Failed to get clock\n");
|
|
return PTR_ERR(data->clk);
|
|
}
|
|
|
|
ret = clk_prepare(data->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (pdata->type == SOC_ARCH_EXYNOS4210 ||
|
|
pdata->type == SOC_ARCH_EXYNOS4412 ||
|
|
pdata->type == SOC_ARCH_EXYNOS5250 ||
|
|
pdata->type == SOC_ARCH_EXYNOS5440)
|
|
data->soc = pdata->type;
|
|
else {
|
|
ret = -EINVAL;
|
|
dev_err(&pdev->dev, "Platform not supported\n");
|
|
goto err_clk;
|
|
}
|
|
|
|
ret = exynos_tmu_initialize(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to initialize TMU\n");
|
|
goto err_clk;
|
|
}
|
|
|
|
exynos_tmu_control(pdev, true);
|
|
|
|
/* Allocate a structure to register with the exynos core thermal */
|
|
sensor_conf = devm_kzalloc(&pdev->dev,
|
|
sizeof(struct thermal_sensor_conf), GFP_KERNEL);
|
|
if (!sensor_conf) {
|
|
dev_err(&pdev->dev, "Failed to allocate registration struct\n");
|
|
ret = -ENOMEM;
|
|
goto err_clk;
|
|
}
|
|
sprintf(sensor_conf->name, "therm_zone%d", data->id);
|
|
sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read;
|
|
sensor_conf->write_emul_temp =
|
|
(int (*)(void *, unsigned long))exynos_tmu_set_emulation;
|
|
sensor_conf->driver_data = data;
|
|
sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] +
|
|
pdata->trigger_enable[1] + pdata->trigger_enable[2]+
|
|
pdata->trigger_enable[3];
|
|
|
|
for (i = 0; i < sensor_conf->trip_data.trip_count; i++) {
|
|
sensor_conf->trip_data.trip_val[i] =
|
|
pdata->threshold + pdata->trigger_levels[i];
|
|
sensor_conf->trip_data.trip_type[i] =
|
|
pdata->trigger_type[i];
|
|
}
|
|
|
|
sensor_conf->trip_data.trigger_falling = pdata->threshold_falling;
|
|
|
|
sensor_conf->cooling_data.freq_clip_count = pdata->freq_tab_count;
|
|
for (i = 0; i < pdata->freq_tab_count; i++) {
|
|
sensor_conf->cooling_data.freq_data[i].freq_clip_max =
|
|
pdata->freq_tab[i].freq_clip_max;
|
|
sensor_conf->cooling_data.freq_data[i].temp_level =
|
|
pdata->freq_tab[i].temp_level;
|
|
}
|
|
sensor_conf->dev = &pdev->dev;
|
|
/* Register the sensor with thermal management interface */
|
|
ret = exynos_register_thermal(sensor_conf);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register thermal interface\n");
|
|
goto err_clk;
|
|
}
|
|
data->reg_conf = sensor_conf;
|
|
|
|
ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
|
|
IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
|
|
goto err_clk;
|
|
}
|
|
|
|
return 0;
|
|
err_clk:
|
|
clk_unprepare(data->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int exynos_tmu_remove(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
|
|
exynos_tmu_control(pdev, false);
|
|
|
|
exynos_unregister_thermal(data->reg_conf);
|
|
|
|
clk_unprepare(data->clk);
|
|
|
|
if (!IS_ERR(data->regulator))
|
|
regulator_disable(data->regulator);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int exynos_tmu_suspend(struct device *dev)
|
|
{
|
|
exynos_tmu_control(to_platform_device(dev), false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_tmu_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
exynos_tmu_initialize(pdev);
|
|
exynos_tmu_control(pdev, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
|
|
exynos_tmu_suspend, exynos_tmu_resume);
|
|
#define EXYNOS_TMU_PM (&exynos_tmu_pm)
|
|
#else
|
|
#define EXYNOS_TMU_PM NULL
|
|
#endif
|
|
|
|
static struct platform_driver exynos_tmu_driver = {
|
|
.driver = {
|
|
.name = "exynos-tmu",
|
|
.owner = THIS_MODULE,
|
|
.pm = EXYNOS_TMU_PM,
|
|
.of_match_table = exynos_tmu_match,
|
|
},
|
|
.probe = exynos_tmu_probe,
|
|
.remove = exynos_tmu_remove,
|
|
};
|
|
|
|
module_platform_driver(exynos_tmu_driver);
|
|
|
|
MODULE_DESCRIPTION("EXYNOS TMU Driver");
|
|
MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:exynos-tmu");
|