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9d6693369f
The SP805 DT binding requires two clocks to be specified, but the Broadcom Cygnus DT currently only specifies one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
624 lines
15 KiB
Text
624 lines
15 KiB
Text
/*
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* BSD LICENSE
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*
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* Copyright(c) 2014 Broadcom Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/bcm-cygnus.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,cygnus";
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model = "Broadcom Cygnus SoC";
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interrupt-parent = <&gic>;
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aliases {
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ethernet0 = ð0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0 0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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};
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/include/ "bcm-cygnus-clock.dtsi"
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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core@19000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0x19000000 0x1000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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clocks = <&periph_clk>;
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};
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gic: interrupt-controller@21000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x21000 0x1000>,
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<0x20100 0x100>;
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};
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L2: cache-controller@22000 {
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compatible = "arm,pl310-cache";
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reg = <0x22000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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};
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axi {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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otp: otp@301c800 {
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compatible = "brcm,ocotp";
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reg = <0x0301c800 0x2c>;
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brcm,ocotp-size = <2048>;
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status = "disabled";
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};
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pcie_phy: phy@301d0a0 {
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compatible = "brcm,cygnus-pcie-phy";
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reg = <0x0301d0a0 0x14>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie0_phy: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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pcie1_phy: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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};
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pinctrl: pinctrl@301d0c8 {
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compatible = "brcm,cygnus-pinmux";
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reg = <0x0301d0c8 0x30>,
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<0x0301d24c 0x2c>;
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spi_0: spi_0 {
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function = "spi0";
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groups = "spi0_grp";
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};
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spi_1: spi_1 {
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function = "spi1";
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groups = "spi1_grp";
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};
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spi_2: spi_2 {
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function = "spi2";
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groups = "spi2_grp";
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};
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};
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mailbox: mailbox@3024024 {
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compatible = "brcm,iproc-mailbox";
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reg = <0x03024024 0x40>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-controller;
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#mbox-cells = <1>;
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};
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gpio_crmu: gpio@3024800 {
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compatible = "brcm,cygnus-crmu-gpio";
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reg = <0x03024800 0x50>,
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<0x03024008 0x18>;
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ngpios = <6>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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interrupt-parent = <&mailbox>;
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interrupts = <0>;
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};
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mdio: mdio@18002000 {
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compatible = "brcm,iproc-mdio";
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reg = <0x18002000 0x8>;
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#size-cells = <0>;
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#address-cells = <1>;
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status = "disabled";
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gphy0: ethernet-phy@0 {
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reg = <0>;
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};
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gphy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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switch: switch@18007000 {
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compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab";
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reg = <0x18007000 0x1000>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phy-handle = <&gphy0>;
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phy-mode = "rgmii";
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};
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port@1 {
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reg = <1>;
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phy-handle = <&gphy1>;
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phy-mode = "rgmii";
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};
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port@8 {
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reg = <8>;
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label = "cpu";
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ethernet = <ð0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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i2c0: i2c@18008000 {
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compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
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reg = <0x18008000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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wdt0: wdt@18009000 {
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compatible = "arm,sp805" , "arm,primecell";
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reg = <0x18009000 0x1000>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&axi81_clk>, <&axi81_clk>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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gpio_ccm: gpio@1800a000 {
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compatible = "brcm,cygnus-ccm-gpio";
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reg = <0x1800a000 0x50>,
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<0x0301d164 0x20>;
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ngpios = <24>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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i2c1: i2c@1800b000 {
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compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
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reg = <0x1800b000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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pcie0: pcie@18012000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18012000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x28000000 0 0x00010000
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0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
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phys = <&pcie0_phy>;
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phy-names = "pcie-phy";
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status = "disabled";
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msi-parent = <&msi0>;
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msi0: msi-controller {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pcie1: pcie@18013000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18013000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x48000000 0 0x00010000
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0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy";
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status = "disabled";
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msi-parent = <&msi1>;
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msi1: msi-controller {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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dma0: dma@18018000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x18018000 0x1000>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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};
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uart0: serial@18020000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x18020000 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&axi81_clk>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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uart1: serial@18021000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x18021000 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&axi81_clk>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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uart2: serial@18022000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x18022000 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&axi81_clk>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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uart3: serial@18023000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x18023000 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&axi81_clk>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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spi0: spi@18028000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x18028000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&spi_0>;
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clocks = <&axi81_clk>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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spi1: spi@18029000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x18029000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&spi_1>;
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clocks = <&axi81_clk>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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spi2: spi@1802a000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x1802a000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&spi_2>;
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clocks = <&axi81_clk>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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rng: rng@18032000 {
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compatible = "brcm,iproc-rng200";
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reg = <0x18032000 0x28>;
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};
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sdhci0: sdhci@18041000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x18041000 0x100>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
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bus-width = <4>;
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sdhci,auto-cmd12;
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status = "disabled";
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};
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eth0: ethernet@18042000 {
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compatible = "brcm,amac";
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reg = <0x18042000 0x1000>,
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<0x18110000 0x1000>;
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reg-names = "amac_base", "idm_base";
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sdhci1: sdhci@18043000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x18043000 0x100>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
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bus-width = <4>;
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sdhci,auto-cmd12;
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status = "disabled";
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};
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nand: nand@18046000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
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reg = <0x18046000 0x600>, <0xf8105408 0x600>,
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<0x18046f00 0x20>;
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reg-names = "nand", "iproc-idm", "iproc-ext";
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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brcm,nand-has-wp;
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};
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ehci0: usb@18048000 {
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compatible = "generic-ehci";
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reg = <0x18048000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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ohci0: usb@18048800 {
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compatible = "generic-ohci";
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reg = <0x18048800 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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clcd: clcd@180a0000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x180a0000 0x1000>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "combined";
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clocks = <&axi41_clk>, <&apb_clk>;
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|
clock-names = "clcdclk", "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
v3d: v3d@180a2000 {
|
|
compatible = "brcm,cygnus-v3d";
|
|
reg = <0x180a2000 0x1000>;
|
|
clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
|
|
clock-names = "v3d_clk";
|
|
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vc4: gpu {
|
|
compatible = "brcm,cygnus-vc4";
|
|
};
|
|
|
|
gpio_asiu: gpio@180a5000 {
|
|
compatible = "brcm,cygnus-asiu-gpio";
|
|
reg = <0x180a5000 0x668>;
|
|
ngpios = <146>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
|
|
interrupt-controller;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-ranges = <&pinctrl 0 42 1>,
|
|
<&pinctrl 1 44 3>,
|
|
<&pinctrl 4 48 1>,
|
|
<&pinctrl 5 50 3>,
|
|
<&pinctrl 8 126 1>,
|
|
<&pinctrl 9 155 1>,
|
|
<&pinctrl 10 152 1>,
|
|
<&pinctrl 11 154 1>,
|
|
<&pinctrl 12 153 1>,
|
|
<&pinctrl 13 127 3>,
|
|
<&pinctrl 16 140 1>,
|
|
<&pinctrl 17 145 7>,
|
|
<&pinctrl 24 130 10>,
|
|
<&pinctrl 34 141 4>,
|
|
<&pinctrl 38 54 1>,
|
|
<&pinctrl 39 56 3>,
|
|
<&pinctrl 42 60 3>,
|
|
<&pinctrl 45 64 3>,
|
|
<&pinctrl 48 68 2>,
|
|
<&pinctrl 50 84 6>,
|
|
<&pinctrl 56 94 6>,
|
|
<&pinctrl 62 72 1>,
|
|
<&pinctrl 63 70 1>,
|
|
<&pinctrl 64 80 1>,
|
|
<&pinctrl 65 74 3>,
|
|
<&pinctrl 68 78 1>,
|
|
<&pinctrl 69 82 1>,
|
|
<&pinctrl 70 156 17>,
|
|
<&pinctrl 87 104 12>,
|
|
<&pinctrl 99 102 2>,
|
|
<&pinctrl 101 90 4>,
|
|
<&pinctrl 105 116 6>,
|
|
<&pinctrl 111 100 2>,
|
|
<&pinctrl 113 122 4>,
|
|
<&pinctrl 123 11 1>,
|
|
<&pinctrl 124 38 4>,
|
|
<&pinctrl 128 43 1>,
|
|
<&pinctrl 129 47 1>,
|
|
<&pinctrl 130 49 1>,
|
|
<&pinctrl 131 53 1>,
|
|
<&pinctrl 132 55 1>,
|
|
<&pinctrl 133 59 1>,
|
|
<&pinctrl 134 63 1>,
|
|
<&pinctrl 135 67 1>,
|
|
<&pinctrl 136 71 1>,
|
|
<&pinctrl 137 73 1>,
|
|
<&pinctrl 138 77 1>,
|
|
<&pinctrl 139 79 1>,
|
|
<&pinctrl 140 81 1>,
|
|
<&pinctrl 141 83 1>,
|
|
<&pinctrl 142 10 1>;
|
|
};
|
|
|
|
ts_adc_syscon: ts_adc_syscon@180a6000 {
|
|
compatible = "brcm,iproc-ts-adc-syscon", "syscon";
|
|
reg = <0x180a6000 0xc30>;
|
|
};
|
|
|
|
touchscreen: touchscreen@180a6000 {
|
|
compatible = "brcm,iproc-touchscreen";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ts_syscon = <&ts_adc_syscon>;
|
|
clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
|
|
clock-names = "tsc_clk";
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc: adc@180a6000 {
|
|
compatible = "brcm,iproc-static-adc";
|
|
#io-channel-cells = <1>;
|
|
io-channel-ranges;
|
|
adc-syscon = <&ts_adc_syscon>;
|
|
clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
|
|
clock-names = "tsc_clk";
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@180aa500 {
|
|
compatible = "brcm,kona-pwm";
|
|
reg = <0x180aa500 0xc4>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
keypad: keypad@180ac000 {
|
|
compatible = "brcm,bcm-keypad";
|
|
reg = <0x180ac000 0x14c>;
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>;
|
|
clock-names = "peri_clk";
|
|
clock-frequency = <31250>;
|
|
pull-up-enabled;
|
|
col-debounce-filter-period = <0>;
|
|
status-debounce-filter-period = <0>;
|
|
row-output-enabled;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|