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3ac395a5b3
The register based driver turned out to be unstable, specially on RPi3a+
but not limited to it. While a fix is being worked on, we roll back to
using firmware based scheme.
Fixes: e1dc2b2e1b ("ARM: bcm283x: Switch V3D over to using the PM driver instead of firmware")
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Link: https://lore.kernel.org/r/20200303173217.3987-1-nsaenzjulienne@suse.de
95 lines
2.1 KiB
Text
95 lines
2.1 KiB
Text
#include "bcm283x.dtsi"
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#include "bcm2835-common.dtsi"
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#include "bcm2835-rpi-common.dtsi"
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/ {
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compatible = "brcm,bcm2837";
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soc {
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ranges = <0x7e000000 0x3f000000 0x1000000>,
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<0x40000000 0x40000000 0x00001000>;
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dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
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local_intc: local_intc@40000000 {
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compatible = "brcm,bcm2836-l1-intc";
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reg = <0x40000000 0x100>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&local_intc>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupt-parent = <&local_intc>;
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interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&local_intc>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
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<1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
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<3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
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<2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
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always-on;
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000d8>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <1>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000e0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <2>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000e8>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <3>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000f0>;
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};
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};
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};
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/* Make the BCM2835-style global interrupt controller be a child of the
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* CPU-local interrupt controller.
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*/
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&intc {
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compatible = "brcm,bcm2836-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-parent = <&local_intc>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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};
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&cpu_thermal {
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coefficients = <(-538) 412000>;
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};
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/* enable thermal sensor with the correct compatible property set */
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&thermal {
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compatible = "brcm,bcm2837-thermal";
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status = "okay";
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};
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