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2bfdd113d0
The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd:
[ 4.854337] m25p80@0 enforce active low on chipselect handle
Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.
The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:
* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.
To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
104 lines
2.1 KiB
Text
104 lines
2.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright 2013 Greg Ungerer <gerg@uclinux.org>
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// Copyright 2011 Freescale Semiconductor, Inc.
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// Copyright 2011 Linaro Ltd.
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/dts-v1/;
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#include "imx50.dtsi"
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/ {
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model = "Freescale i.MX50 Evaluation Kit";
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compatible = "fsl,imx50-evk", "fsl,imx50";
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memory@70000000 {
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device_type = "memory";
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reg = <0x70000000 0x80000000>;
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};
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};
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&cspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_cspi>;
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cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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flash: m25p32@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "m25p32", "jedec,spi-nor";
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spi-max-frequency = <25000000>;
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reg = <1>;
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partition@0 {
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label = "bootloader";
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reg = <0x0 0x100000>;
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read-only;
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};
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partition@100000 {
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label = "kernel";
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reg = <0x100000 0x300000>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&iomuxc {
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imx50-evk {
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pinctrl_cspi: cspigrp {
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fsl,pins = <
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MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
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MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
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MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
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MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
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MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX50_PAD_SSI_RXFS__FEC_MDC 0x80
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MX50_PAD_SSI_RXC__FEC_MDIO 0x80
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MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
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MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
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MX50_PAD_DISP_D2__FEC_RX_DV 0x80
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MX50_PAD_DISP_D3__FEC_RDATA_1 0x80
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MX50_PAD_DISP_D4__FEC_RDATA_0 0x80
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MX50_PAD_DISP_D5__FEC_TX_EN 0x80
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MX50_PAD_DISP_D6__FEC_TDATA_1 0x80
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MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4
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MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4
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MX50_PAD_UART1_RTS__UART1_RTS 0x1e4
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MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
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>;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usbh1 {
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status = "okay";
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};
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&usbotg {
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status = "okay";
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};
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