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73106f75bf
Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller IP which typically connects to an eMMC chip (because unlike the SDIO controller the SDHC controller has an 8-bit bus interface). On Meson8, Meson8b and Meson8m2 the clock inputs are all the same. However, Meson8m2 seems to have an improved version of the SHDC controller IP which doesn't require the driver to wait manually for a flush of a DMA transfer. Thus every SoC has it's own compatible string so if more difference are discovered they can be implemented. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200620163654.37207-2-martin.blumenstingl@googlemail.com
640 lines
14 KiB
Text
640 lines
14 KiB
Text
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*/
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#include <dt-bindings/clock/meson8-ddr-clkc.h>
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/gpio/meson8b-gpio.h>
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#include <dt-bindings/power/meson8-power.h>
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#include <dt-bindings/reset/amlogic,meson8b-reset.h>
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#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
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#include "meson.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x200>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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};
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cpu1: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x201>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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};
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cpu2: cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x202>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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};
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cpu3: cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x203>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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};
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};
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-96000000 {
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opp-hz = /bits/ 64 <96000000>;
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opp-microvolt = <860000>;
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};
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opp-192000000 {
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opp-hz = /bits/ 64 <192000000>;
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opp-microvolt = <860000>;
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};
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opp-312000000 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <860000>;
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <860000>;
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};
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opp-504000000 {
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opp-hz = /bits/ 64 <504000000>;
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opp-microvolt = <860000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <860000>;
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};
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opp-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <860000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <900000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1140000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1140000>;
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};
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opp-1320000000 {
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opp-hz = /bits/ 64 <1320000000>;
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opp-microvolt = <1140000>;
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};
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opp-1488000000 {
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opp-hz = /bits/ 64 <1488000000>;
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opp-microvolt = <1140000>;
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};
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opp-1536000000 {
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opp-hz = /bits/ 64 <1536000000>;
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opp-microvolt = <1140000>;
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};
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};
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gpu_opp_table: gpu-opp-table {
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compatible = "operating-points-v2";
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opp-255000000 {
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opp-hz = /bits/ 64 <255000000>;
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opp-microvolt = <1100000>;
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};
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opp-364285714 {
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opp-hz = /bits/ 64 <364285714>;
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opp-microvolt = <1100000>;
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};
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opp-425000000 {
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opp-hz = /bits/ 64 <425000000>;
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opp-microvolt = <1100000>;
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};
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opp-510000000 {
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opp-hz = /bits/ 64 <510000000>;
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opp-microvolt = <1100000>;
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};
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opp-637500000 {
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opp-hz = /bits/ 64 <637500000>;
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opp-microvolt = <1100000>;
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turbo-mode;
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};
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};
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pmu {
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compatible = "arm,cortex-a5-pmu";
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* 2 MiB reserved for Hardware ROM Firmware? */
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hwrom@0 {
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reg = <0x0 0x200000>;
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no-map;
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};
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};
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mmcbus: bus@c8000000 {
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compatible = "simple-bus";
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reg = <0xc8000000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xc8000000 0x8000>;
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ddr_clkc: clock-controller@400 {
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compatible = "amlogic,meson8b-ddr-clkc";
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reg = <0x400 0x20>;
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clocks = <&xtal>;
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clock-names = "xtal";
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#clock-cells = <1>;
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};
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dmcbus: bus@6000 {
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compatible = "simple-bus";
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reg = <0x6000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x6000 0x400>;
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canvas: video-lut@48 {
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compatible = "amlogic,meson8b-canvas",
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"amlogic,canvas";
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reg = <0x48 0x14>;
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};
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};
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};
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apb: bus@d0000000 {
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compatible = "simple-bus";
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reg = <0xd0000000 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xd0000000 0x200000>;
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mali: gpu@c0000 {
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compatible = "amlogic,meson8b-mali", "arm,mali-450";
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reg = <0xc0000 0x40000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp", "gpmmu", "pp", "pmu",
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"pp0", "ppmmu0", "pp1", "ppmmu1";
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resets = <&reset RESET_MALI>;
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
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clock-names = "bus", "core";
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operating-points-v2 = <&gpu_opp_table>;
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};
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};
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}; /* end of / */
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&aobus {
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pmu: pmu@e0 {
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compatible = "amlogic,meson8b-pmu", "syscon";
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reg = <0xe0 0x18>;
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};
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pinctrl_aobus: pinctrl@84 {
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compatible = "amlogic,meson8b-aobus-pinctrl";
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reg = <0x84 0xc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio_ao: ao-bank@14 {
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reg = <0x14 0x4>,
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<0x2c 0x4>,
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<0x24 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 16>;
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};
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uart_ao_a_pins: uart_ao_a {
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mux {
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groups = "uart_tx_ao_a", "uart_rx_ao_a";
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function = "uart_ao";
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bias-disable;
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};
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};
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ir_recv_pins: remote {
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mux {
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groups = "remote_input";
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function = "remote";
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bias-disable;
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};
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};
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};
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};
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&cbus {
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reset: reset-controller@4404 {
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compatible = "amlogic,meson8b-reset";
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reg = <0x4404 0x9c>;
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#reset-cells = <1>;
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};
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analog_top: analog-top@81a8 {
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compatible = "amlogic,meson8b-analog-top", "syscon";
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reg = <0x81a8 0x14>;
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};
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pwm_ef: pwm@86c0 {
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compatible = "amlogic,meson8b-pwm";
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reg = <0x86c0 0x10>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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clock-measure@8758 {
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compatible = "amlogic,meson8b-clk-measure";
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reg = <0x8758 0x1c>;
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};
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pinctrl_cbus: pinctrl@9880 {
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compatible = "amlogic,meson8b-cbus-pinctrl";
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reg = <0x9880 0x10>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio: banks@80b0 {
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reg = <0x80b0 0x28>,
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<0x80e8 0x18>,
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<0x8120 0x18>,
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<0x8030 0x38>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_cbus 0 0 83>;
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};
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eth_rgmii_pins: eth-rgmii {
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mux {
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groups = "eth_tx_clk",
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"eth_tx_en",
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"eth_txd1_0",
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"eth_txd0_0",
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"eth_rx_clk",
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"eth_rx_dv",
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"eth_rxd1",
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"eth_rxd0",
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"eth_mdio_en",
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"eth_mdc",
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"eth_ref_clk",
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"eth_txd2",
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"eth_txd3",
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"eth_rxd3",
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"eth_rxd2";
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function = "ethernet";
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bias-disable;
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};
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};
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eth_rmii_pins: eth-rmii {
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mux {
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groups = "eth_tx_en",
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"eth_txd1_0",
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"eth_txd0_0",
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"eth_rx_clk",
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"eth_rx_dv",
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"eth_rxd1",
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"eth_rxd0",
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"eth_mdio_en",
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"eth_mdc";
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function = "ethernet";
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bias-disable;
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};
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};
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i2c_a_pins: i2c-a {
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mux {
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groups = "i2c_sda_a", "i2c_sck_a";
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function = "i2c_a";
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bias-disable;
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};
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};
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sd_b_pins: sd-b {
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mux {
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groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
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"sd_d3_b", "sd_clk_b", "sd_cmd_b";
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function = "sd_b";
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bias-disable;
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};
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};
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sdxc_c_pins: sdxc-c {
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mux {
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groups = "sdxc_d0_c", "sdxc_d13_c",
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"sdxc_d47_c", "sdxc_clk_c",
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"sdxc_cmd_c";
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function = "sdxc_c";
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bias-pull-up;
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};
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};
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pwm_c1_pins: pwm-c1 {
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mux {
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groups = "pwm_c1";
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function = "pwm_c";
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bias-disable;
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};
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};
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pwm_d_pins: pwm-d {
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mux {
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groups = "pwm_d";
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function = "pwm_d";
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bias-disable;
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};
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};
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uart_b0_pins: uart-b0 {
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mux {
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groups = "uart_tx_b0",
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"uart_rx_b0";
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function = "uart_b";
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bias-disable;
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};
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};
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uart_b0_cts_rts_pins: uart-b0-cts-rts {
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mux {
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groups = "uart_cts_b0",
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"uart_rts_b0";
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function = "uart_b";
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bias-disable;
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};
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};
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};
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};
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&ahb_sram {
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smp-sram@1ff80 {
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compatible = "amlogic,meson8b-smp-sram";
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reg = <0x1ff80 0x8>;
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};
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};
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&efuse {
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compatible = "amlogic,meson8b-efuse";
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clocks = <&clkc CLKID_EFUSE>;
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clock-names = "core";
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temperature_calib: calib@1f4 {
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/* only the upper two bytes are relevant */
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reg = <0x1f4 0x4>;
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};
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};
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ðmac {
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compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
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reg = <0xc9410000 0x10000
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0xc1108140 0x4>;
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
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rx-fifo-depth = <4096>;
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tx-fifo-depth = <2048>;
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resets = <&reset RESET_ETHERNET>;
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reset-names = "stmmaceth";
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power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
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};
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&gpio_intc {
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compatible = "amlogic,meson-gpio-intc",
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"amlogic,meson8b-gpio-intc";
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status = "okay";
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};
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&hhi {
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clkc: clock-controller {
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compatible = "amlogic,meson8b-clkc";
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clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
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clock-names = "xtal", "ddr_pll";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pwrc: power-controller {
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compatible = "amlogic,meson8b-pwrc";
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#power-domain-cells = <1>;
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amlogic,ao-sysctrl = <&pmu>;
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resets = <&reset RESET_DBLK>,
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<&reset RESET_PIC_DC>,
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<&reset RESET_HDMI_APB>,
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<&reset RESET_HDMI_SYSTEM_RESET>,
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<&reset RESET_VENCI>,
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<&reset RESET_VENCP>,
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<&reset RESET_VDAC_4>,
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<&reset RESET_VENCL>,
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<&reset RESET_VIU>,
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<&reset RESET_VENC>,
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<&reset RESET_RDMA>;
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reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
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"venci", "vencp", "vdac", "vencl", "viu",
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"venc", "rdma";
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clocks = <&clkc CLKID_VPU>;
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clock-names = "vpu";
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assigned-clocks = <&clkc CLKID_VPU>;
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assigned-clock-rates = <182142857>;
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};
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};
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&hwrng {
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compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
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clocks = <&clkc CLKID_RNG0>;
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clock-names = "core";
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};
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&i2c_AO {
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clocks = <&clkc CLKID_CLK81>;
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};
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&i2c_A {
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clocks = <&clkc CLKID_I2C>;
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};
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|
|
&i2c_B {
|
|
clocks = <&clkc CLKID_I2C>;
|
|
};
|
|
|
|
&L2 {
|
|
arm,data-latency = <3 3 3>;
|
|
arm,tag-latency = <2 2 2>;
|
|
arm,filter-ranges = <0x100000 0xc0000000>;
|
|
prefetch-data = <1>;
|
|
prefetch-instr = <1>;
|
|
arm,shared-override;
|
|
};
|
|
|
|
&periph {
|
|
scu@0 {
|
|
compatible = "arm,cortex-a5-scu";
|
|
reg = <0x0 0x100>;
|
|
};
|
|
|
|
timer@200 {
|
|
compatible = "arm,cortex-a5-global-timer";
|
|
reg = <0x200 0x20>;
|
|
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
|
clocks = <&clkc CLKID_PERIPH>;
|
|
|
|
/*
|
|
* the arm_global_timer driver currently does not handle clock
|
|
* rate changes. Keep it disabled for now.
|
|
*/
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@600 {
|
|
compatible = "arm,cortex-a5-twd-timer";
|
|
reg = <0x600 0x20>;
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
|
clocks = <&clkc CLKID_PERIPH>;
|
|
};
|
|
};
|
|
|
|
&pwm_ab {
|
|
compatible = "amlogic,meson8b-pwm";
|
|
};
|
|
|
|
&pwm_cd {
|
|
compatible = "amlogic,meson8b-pwm";
|
|
};
|
|
|
|
&rtc {
|
|
compatible = "amlogic,meson8b-rtc";
|
|
resets = <&reset RESET_RTC>;
|
|
};
|
|
|
|
&saradc {
|
|
compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
|
|
clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
|
|
clock-names = "clkin", "core";
|
|
amlogic,hhi-sysctrl = <&hhi>;
|
|
nvmem-cells = <&temperature_calib>;
|
|
nvmem-cell-names = "temperature_calib";
|
|
};
|
|
|
|
&sdhc {
|
|
compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
|
|
clocks = <&xtal>,
|
|
<&clkc CLKID_FCLK_DIV4>,
|
|
<&clkc CLKID_FCLK_DIV3>,
|
|
<&clkc CLKID_FCLK_DIV5>,
|
|
<&clkc CLKID_SDHC>;
|
|
clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
|
|
};
|
|
|
|
&sdio {
|
|
compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
|
|
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
|
|
clock-names = "core", "clkin";
|
|
};
|
|
|
|
&timer_abcde {
|
|
clocks = <&xtal>, <&clkc CLKID_CLK81>;
|
|
clock-names = "xtal", "pclk";
|
|
};
|
|
|
|
&uart_AO {
|
|
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
|
|
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
|
|
clock-names = "baud", "xtal", "pclk";
|
|
};
|
|
|
|
&uart_A {
|
|
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
|
|
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
|
|
clock-names = "baud", "xtal", "pclk";
|
|
};
|
|
|
|
&uart_B {
|
|
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
|
|
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
|
|
clock-names = "baud", "xtal", "pclk";
|
|
};
|
|
|
|
&uart_C {
|
|
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
|
|
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
|
|
clock-names = "baud", "xtal", "pclk";
|
|
};
|
|
|
|
&usb0 {
|
|
compatible = "amlogic,meson8b-usb", "snps,dwc2";
|
|
clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
|
|
clock-names = "otg";
|
|
};
|
|
|
|
&usb1 {
|
|
compatible = "amlogic,meson8b-usb", "snps,dwc2";
|
|
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
|
clock-names = "otg";
|
|
};
|
|
|
|
&usb0_phy {
|
|
compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
|
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
|
|
clock-names = "usb_general", "usb";
|
|
resets = <&reset RESET_USB_OTG>;
|
|
};
|
|
|
|
&usb1_phy {
|
|
compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
|
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
|
|
clock-names = "usb_general", "usb";
|
|
resets = <&reset RESET_USB_OTG>;
|
|
};
|
|
|
|
&wdt {
|
|
compatible = "amlogic,meson8b-wdt";
|
|
};
|