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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
377 lines
9.2 KiB
C
377 lines
9.2 KiB
C
/* -*- mode: c; c-basic-offset: 8 -*- */
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/* NCR Quad 720 MCA SCSI Driver
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*
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* Copyright (C) 2003 by James.Bottomley@HansenPartnership.com
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*/
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#include <linux/blkdev.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mca.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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#include "ncr53c8xx.h"
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#include "NCR_Q720.h"
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static struct ncr_chip q720_chip __initdata = {
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.revision_id = 0x0f,
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.burst_max = 3,
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.offset_max = 8,
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.nr_divisor = 4,
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.features = FE_WIDE | FE_DIFF | FE_VARCLK,
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};
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MODULE_AUTHOR("James Bottomley");
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MODULE_DESCRIPTION("NCR Quad 720 SCSI Driver");
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MODULE_LICENSE("GPL");
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#define NCR_Q720_VERSION "0.9"
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/* We needs this helper because we have up to four hosts per struct device */
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struct NCR_Q720_private {
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struct device *dev;
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void __iomem * mem_base;
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__u32 phys_mem_base;
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__u32 mem_size;
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__u8 irq;
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__u8 siops;
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__u8 irq_enable;
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struct Scsi_Host *hosts[4];
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};
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static struct scsi_host_template NCR_Q720_tpnt = {
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.module = THIS_MODULE,
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.proc_name = "NCR_Q720",
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};
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static irqreturn_t
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NCR_Q720_intr(int irq, void *data)
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{
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struct NCR_Q720_private *p = (struct NCR_Q720_private *)data;
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__u8 sir = (readb(p->mem_base + 0x0d) & 0xf0) >> 4;
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__u8 siop;
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sir |= ~p->irq_enable;
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if(sir == 0xff)
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return IRQ_NONE;
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while((siop = ffz(sir)) < p->siops) {
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sir |= 1<<siop;
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ncr53c8xx_intr(irq, p->hosts[siop]);
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}
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return IRQ_HANDLED;
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}
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static int __init
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NCR_Q720_probe_one(struct NCR_Q720_private *p, int siop,
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int irq, int slot, __u32 paddr, void __iomem *vaddr)
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{
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struct ncr_device device;
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__u8 scsi_id;
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static int unit = 0;
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__u8 scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1);
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__u8 differential = readb(vaddr + NCR_Q720_SCSR_OFFSET) & 0x20;
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__u8 version;
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int error;
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scsi_id = scsr1 >> 4;
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/* enable burst length 16 (FIXME: should allow this) */
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scsr1 |= 0x02;
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/* force a siop reset */
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scsr1 |= 0x04;
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writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1);
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udelay(10);
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version = readb(vaddr + 0x18) >> 4;
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memset(&device, 0, sizeof(struct ncr_device));
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/* Initialise ncr_device structure with items required by ncr_attach. */
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device.chip = q720_chip;
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device.chip.revision_id = version;
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device.host_id = scsi_id;
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device.dev = p->dev;
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device.slot.base = paddr;
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device.slot.base_c = paddr;
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device.slot.base_v = vaddr;
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device.slot.irq = irq;
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device.differential = differential ? 2 : 0;
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printk("Q720 probe unit %d (siop%d) at 0x%lx, diff = %d, vers = %d\n", unit, siop,
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(unsigned long)paddr, differential, version);
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p->hosts[siop] = ncr_attach(&NCR_Q720_tpnt, unit++, &device);
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if (!p->hosts[siop])
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goto fail;
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p->irq_enable |= (1<<siop);
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scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1);
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/* clear the disable interrupt bit */
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scsr1 &= ~0x01;
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writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1);
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error = scsi_add_host(p->hosts[siop], p->dev);
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if (error)
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ncr53c8xx_release(p->hosts[siop]);
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else
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scsi_scan_host(p->hosts[siop]);
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return error;
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fail:
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return -ENODEV;
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}
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/* Detect a Q720 card. Note, because of the setup --- the chips are
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* essentially connectecd to the MCA bus independently, it is easier
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* to set them up as two separate host adapters, rather than one
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* adapter with two channels */
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static int __init
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NCR_Q720_probe(struct device *dev)
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{
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struct NCR_Q720_private *p;
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static int banner = 1;
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struct mca_device *mca_dev = to_mca_device(dev);
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int slot = mca_dev->slot;
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int found = 0;
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int irq, i, siops;
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__u8 pos2, pos4, asr2, asr9, asr10;
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__u16 io_base;
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__u32 base_addr, mem_size;
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void __iomem *mem_base;
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p = kzalloc(sizeof(*p), GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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pos2 = mca_device_read_pos(mca_dev, 2);
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/* enable device */
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pos2 |= NCR_Q720_POS2_BOARD_ENABLE | NCR_Q720_POS2_INTERRUPT_ENABLE;
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mca_device_write_pos(mca_dev, 2, pos2);
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io_base = (pos2 & NCR_Q720_POS2_IO_MASK) << NCR_Q720_POS2_IO_SHIFT;
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if(banner) {
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printk(KERN_NOTICE "NCR Q720: Driver Version " NCR_Q720_VERSION "\n"
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"NCR Q720: Copyright (c) 2003 by James.Bottomley@HansenPartnership.com\n"
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"NCR Q720:\n");
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banner = 0;
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}
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io_base = mca_device_transform_ioport(mca_dev, io_base);
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/* OK, this is phase one of the bootstrap, we now know the
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* I/O space base address. All the configuration registers
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* are mapped here (including pos) */
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/* sanity check I/O mapping */
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i = inb(io_base) | (inb(io_base+1)<<8);
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if(i != NCR_Q720_MCA_ID) {
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printk(KERN_ERR "NCR_Q720, adapter failed to I/O map registers correctly at 0x%x(0x%x)\n", io_base, i);
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kfree(p);
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return -ENODEV;
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}
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/* Phase II, find the ram base and memory map the board register */
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pos4 = inb(io_base + 4);
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/* enable streaming data */
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pos4 |= 0x01;
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outb(pos4, io_base + 4);
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base_addr = (pos4 & 0x7e) << 20;
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base_addr += (pos4 & 0x80) << 23;
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asr10 = inb(io_base + 0x12);
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base_addr += (asr10 & 0x80) << 24;
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base_addr += (asr10 & 0x70) << 23;
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/* OK, got the base addr, now we need to find the ram size,
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* enable and map it */
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asr9 = inb(io_base + 0x11);
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i = (asr9 & 0xc0) >> 6;
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if(i == 0)
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mem_size = 1024;
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else
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mem_size = 1 << (19 + i);
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/* enable the sram mapping */
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asr9 |= 0x20;
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/* disable the rom mapping */
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asr9 &= ~0x10;
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outb(asr9, io_base + 0x11);
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if(!request_mem_region(base_addr, mem_size, "NCR_Q720")) {
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printk(KERN_ERR "NCR_Q720: Failed to claim memory region 0x%lx\n-0x%lx",
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(unsigned long)base_addr,
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(unsigned long)(base_addr + mem_size));
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goto out_free;
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}
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if (dma_declare_coherent_memory(dev, base_addr, base_addr,
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mem_size, DMA_MEMORY_MAP)
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!= DMA_MEMORY_MAP) {
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printk(KERN_ERR "NCR_Q720: DMA declare memory failed\n");
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goto out_release_region;
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}
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/* The first 1k of the memory buffer is a memory map of the registers
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*/
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mem_base = dma_mark_declared_memory_occupied(dev, base_addr,
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1024);
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if (IS_ERR(mem_base)) {
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printk("NCR_Q720 failed to reserve memory mapped region\n");
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goto out_release;
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}
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/* now also enable accesses in asr 2 */
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asr2 = inb(io_base + 0x0a);
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asr2 |= 0x01;
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outb(asr2, io_base + 0x0a);
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/* get the number of SIOPs (this should be 2 or 4) */
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siops = ((asr2 & 0xe0) >> 5) + 1;
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/* sanity check mapping (again) */
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i = readw(mem_base);
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if(i != NCR_Q720_MCA_ID) {
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printk(KERN_ERR "NCR_Q720, adapter failed to memory map registers correctly at 0x%lx(0x%x)\n", (unsigned long)base_addr, i);
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goto out_release;
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}
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irq = readb(mem_base + 5) & 0x0f;
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/* now do the bus related transforms */
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irq = mca_device_transform_irq(mca_dev, irq);
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printk(KERN_NOTICE "NCR Q720: found in slot %d irq = %d mem base = 0x%lx siops = %d\n", slot, irq, (unsigned long)base_addr, siops);
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printk(KERN_NOTICE "NCR Q720: On board ram %dk\n", mem_size/1024);
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p->dev = dev;
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p->mem_base = mem_base;
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p->phys_mem_base = base_addr;
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p->mem_size = mem_size;
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p->irq = irq;
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p->siops = siops;
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if (request_irq(irq, NCR_Q720_intr, IRQF_SHARED, "NCR_Q720", p)) {
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printk(KERN_ERR "NCR_Q720: request irq %d failed\n", irq);
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goto out_release;
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}
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/* disable all the siop interrupts */
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for(i = 0; i < siops; i++) {
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void __iomem *reg_scsr1 = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET
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+ i*NCR_Q720_SIOP_SHIFT + NCR_Q720_SCSR_OFFSET + 1;
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__u8 scsr1 = readb(reg_scsr1);
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scsr1 |= 0x01;
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writeb(scsr1, reg_scsr1);
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}
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/* plumb in all 720 chips */
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for (i = 0; i < siops; i++) {
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void __iomem *siop_v_base = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET
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+ i*NCR_Q720_SIOP_SHIFT;
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__u32 siop_p_base = base_addr + NCR_Q720_CHIP_REGISTER_OFFSET
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+ i*NCR_Q720_SIOP_SHIFT;
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__u16 port = io_base + NCR_Q720_CHIP_REGISTER_OFFSET
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+ i*NCR_Q720_SIOP_SHIFT;
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int err;
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outb(0xff, port + 0x40);
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outb(0x07, port + 0x41);
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if ((err = NCR_Q720_probe_one(p, i, irq, slot,
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siop_p_base, siop_v_base)) != 0)
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printk("Q720: SIOP%d: probe failed, error = %d\n",
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i, err);
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else
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found++;
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}
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if (!found) {
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kfree(p);
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return -ENODEV;
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}
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mca_device_set_claim(mca_dev, 1);
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mca_device_set_name(mca_dev, "NCR_Q720");
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dev_set_drvdata(dev, p);
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return 0;
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out_release:
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dma_release_declared_memory(dev);
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out_release_region:
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release_mem_region(base_addr, mem_size);
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out_free:
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kfree(p);
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return -ENODEV;
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}
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static void __exit
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NCR_Q720_remove_one(struct Scsi_Host *host)
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{
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scsi_remove_host(host);
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ncr53c8xx_release(host);
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}
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static int __exit
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NCR_Q720_remove(struct device *dev)
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{
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struct NCR_Q720_private *p = dev_get_drvdata(dev);
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int i;
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for (i = 0; i < p->siops; i++)
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if(p->hosts[i])
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NCR_Q720_remove_one(p->hosts[i]);
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dma_release_declared_memory(dev);
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release_mem_region(p->phys_mem_base, p->mem_size);
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free_irq(p->irq, p);
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kfree(p);
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return 0;
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}
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static short NCR_Q720_id_table[] = { NCR_Q720_MCA_ID, 0 };
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static struct mca_driver NCR_Q720_driver = {
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.id_table = NCR_Q720_id_table,
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.driver = {
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.name = "NCR_Q720",
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.bus = &mca_bus_type,
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.probe = NCR_Q720_probe,
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.remove = __devexit_p(NCR_Q720_remove),
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},
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};
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static int __init
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NCR_Q720_init(void)
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{
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int ret = ncr53c8xx_init();
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if (!ret)
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ret = mca_register_driver(&NCR_Q720_driver);
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if (ret)
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ncr53c8xx_exit();
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return ret;
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}
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static void __exit
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NCR_Q720_exit(void)
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{
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mca_unregister_driver(&NCR_Q720_driver);
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ncr53c8xx_exit();
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}
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module_init(NCR_Q720_init);
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module_exit(NCR_Q720_exit);
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