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![Suresh Siddha](/assets/img/avatar_default.png)
On the platforms which are x2apic and interrupt-remapping capable, Linux kernel is enabling x2apic even if the BIOS doesn't. This is to take advantage of the features that x2apic brings in. Some of the OEM platforms are running into issues because of this, as their bios is not x2apic aware. For example, this was resulting in interrupt migration issues on one of the platforms. Also if the BIOS SMI handling uses APIC interface to send SMI's, then the BIOS need to be aware of x2apic mode that OS has enabled. On some of these platforms, BIOS doesn't have a HW mechanism to turnoff the x2apic feature to prevent OS from enabling it. To resolve this mess, recent changes to the VT-d2 specification: http://download.intel.com/technology/computing/vptech/Intel(r)_VT_for_Direct_IO.pdf includes a mechanism that provides BIOS a way to request system software to opt out of enabling x2apic mode. Look at the x2apic optout flag in the DMAR tables before enabling the x2apic mode in the platform. Also print a warning that we have disabled x2apic based on the BIOS request. Kernel boot parameter "intremap=no_x2apic_optout" can be used to override the BIOS x2apic optout request. Signed-off-by: Youquan Song <youquan.song@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: yinghai@kernel.org Cc: joerg.roedel@amd.com Cc: tony.luck@intel.com Cc: dwmw2@infradead.org Link: http://lkml.kernel.org/r/20110824001456.171766616@sbsiddha-desk.sc.intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
245 lines
6.3 KiB
C
245 lines
6.3 KiB
C
/*
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* Copyright (c) 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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* Copyright (C) Ashok Raj <ashok.raj@intel.com>
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* Copyright (C) Shaohua Li <shaohua.li@intel.com>
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*/
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#ifndef __DMAR_H__
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#define __DMAR_H__
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#include <linux/acpi.h>
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#include <linux/types.h>
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#include <linux/msi.h>
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#include <linux/irqreturn.h>
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/* DMAR Flags */
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#define DMAR_INTR_REMAP 0x1
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#define DMAR_X2APIC_OPT_OUT 0x2
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struct intel_iommu;
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#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
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extern struct acpi_table_header *dmar_tbl;
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struct dmar_drhd_unit {
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struct list_head list; /* list of drhd units */
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struct acpi_dmar_header *hdr; /* ACPI header */
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u64 reg_base_addr; /* register base address*/
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struct pci_dev **devices; /* target device array */
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int devices_cnt; /* target device count */
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u16 segment; /* PCI domain */
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u8 ignored:1; /* ignore drhd */
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u8 include_all:1;
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struct intel_iommu *iommu;
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};
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extern struct list_head dmar_drhd_units;
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#define for_each_drhd_unit(drhd) \
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list_for_each_entry(drhd, &dmar_drhd_units, list)
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#define for_each_active_iommu(i, drhd) \
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list_for_each_entry(drhd, &dmar_drhd_units, list) \
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if (i=drhd->iommu, drhd->ignored) {} else
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#define for_each_iommu(i, drhd) \
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list_for_each_entry(drhd, &dmar_drhd_units, list) \
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if (i=drhd->iommu, 0) {} else
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extern int dmar_table_init(void);
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extern int dmar_dev_scope_init(void);
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/* Intel IOMMU detection */
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extern int detect_intel_iommu(void);
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extern int enable_drhd_fault_handling(void);
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extern int parse_ioapics_under_ir(void);
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extern int alloc_iommu(struct dmar_drhd_unit *);
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#else
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static inline int detect_intel_iommu(void)
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{
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return -ENODEV;
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}
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static inline int dmar_table_init(void)
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{
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return -ENODEV;
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}
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static inline int enable_drhd_fault_handling(void)
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{
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return -1;
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}
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#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
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struct irte {
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union {
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struct {
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__u64 present : 1,
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fpd : 1,
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dst_mode : 1,
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redir_hint : 1,
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trigger_mode : 1,
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dlvry_mode : 3,
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avail : 4,
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__reserved_1 : 4,
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vector : 8,
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__reserved_2 : 8,
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dest_id : 32;
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};
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__u64 low;
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};
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union {
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struct {
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__u64 sid : 16,
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sq : 2,
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svt : 2,
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__reserved_3 : 44;
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};
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__u64 high;
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};
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};
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#ifdef CONFIG_INTR_REMAP
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extern int intr_remapping_enabled;
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extern int intr_remapping_supported(void);
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extern int enable_intr_remapping(void);
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extern void disable_intr_remapping(void);
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extern int reenable_intr_remapping(int);
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extern int get_irte(int irq, struct irte *entry);
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extern int modify_irte(int irq, struct irte *irte_modified);
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extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
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extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
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u16 sub_handle);
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extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
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extern int free_irte(int irq);
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extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
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extern struct intel_iommu *map_ioapic_to_ir(int apic);
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extern struct intel_iommu *map_hpet_to_ir(u8 id);
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extern int set_ioapic_sid(struct irte *irte, int apic);
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extern int set_hpet_sid(struct irte *irte, u8 id);
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extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
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#else
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static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
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{
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return -1;
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}
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static inline int modify_irte(int irq, struct irte *irte_modified)
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{
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return -1;
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}
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static inline int free_irte(int irq)
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{
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return -1;
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}
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static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
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{
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return -1;
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}
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static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
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u16 sub_handle)
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{
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return -1;
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}
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static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
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{
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return NULL;
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}
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static inline struct intel_iommu *map_ioapic_to_ir(int apic)
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{
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return NULL;
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}
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static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
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{
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return NULL;
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}
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static inline int set_ioapic_sid(struct irte *irte, int apic)
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{
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return 0;
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}
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static inline int set_hpet_sid(struct irte *irte, u8 id)
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{
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return -1;
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}
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static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
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{
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return 0;
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}
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#define intr_remapping_enabled (0)
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static inline int enable_intr_remapping(void)
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{
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return -1;
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}
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static inline void disable_intr_remapping(void)
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{
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}
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static inline int reenable_intr_remapping(int eim)
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{
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return 0;
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}
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#endif
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enum {
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IRQ_REMAP_XAPIC_MODE,
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IRQ_REMAP_X2APIC_MODE,
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};
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/* Can't use the common MSI interrupt functions
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* since DMAR is not a pci device
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*/
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struct irq_data;
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extern void dmar_msi_unmask(struct irq_data *data);
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extern void dmar_msi_mask(struct irq_data *data);
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extern void dmar_msi_read(int irq, struct msi_msg *msg);
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extern void dmar_msi_write(int irq, struct msi_msg *msg);
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extern int dmar_set_interrupt(struct intel_iommu *iommu);
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extern irqreturn_t dmar_fault(int irq, void *dev_id);
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extern int arch_setup_dmar_msi(unsigned int irq);
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#ifdef CONFIG_DMAR
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extern int iommu_detected, no_iommu;
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extern struct list_head dmar_rmrr_units;
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struct dmar_rmrr_unit {
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struct list_head list; /* list of rmrr units */
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struct acpi_dmar_header *hdr; /* ACPI header */
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u64 base_address; /* reserved base address*/
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u64 end_address; /* reserved end address */
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struct pci_dev **devices; /* target devices */
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int devices_cnt; /* target device count */
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};
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#define for_each_rmrr_units(rmrr) \
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list_for_each_entry(rmrr, &dmar_rmrr_units, list)
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struct dmar_atsr_unit {
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struct list_head list; /* list of ATSR units */
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struct acpi_dmar_header *hdr; /* ACPI header */
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struct pci_dev **devices; /* target devices */
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int devices_cnt; /* target device count */
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u8 include_all:1; /* include all ports */
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};
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extern int intel_iommu_init(void);
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#else /* !CONFIG_DMAR: */
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static inline int intel_iommu_init(void) { return -ENODEV; }
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#endif /* CONFIG_DMAR */
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#endif /* __DMAR_H__ */
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