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![Prashant Malani](/assets/img/avatar_default.png)
The comment decribing the IPC timeout hadn't been updated when the
actual timeout was changed from 3 to 5 seconds in
commit a7d53dbbc7
("platform/x86: intel_scu_ipc: Increase virtual
timeout from 3 to 5 seconds") .
Since the value is anyway updated to 10s now, take this opportunity to
update the value in the comment too.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Cc: Benson Leung <bleung@chromium.org>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20210928101932.2543937-4-pmalani@chromium.org
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
712 lines
19 KiB
C
712 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for the Intel SCU IPC mechanism
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*
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* (C) Copyright 2008-2010,2015 Intel Corporation
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* Author: Sreedhara DS (sreedhara.ds@intel.com)
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*
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* SCU running in ARC processor communicates with other entity running in IA
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* core through IPC mechanism which in turn messaging between IA core ad SCU.
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* SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
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* SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
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* IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
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* along with other APIs.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <asm/intel_scu_ipc.h>
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/* IPC defines the following message types */
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#define IPCMSG_PCNTRL 0xff /* Power controller unit read/write */
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/* Command id associated with message IPCMSG_PCNTRL */
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#define IPC_CMD_PCNTRL_W 0 /* Register write */
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#define IPC_CMD_PCNTRL_R 1 /* Register read */
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#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
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/*
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* IPC register summary
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*
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* IPC register blocks are memory mapped at fixed address of PCI BAR 0.
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* To read or write information to the SCU, driver writes to IPC-1 memory
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* mapped registers. The following is the IPC mechanism
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*
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* 1. IA core cDMI interface claims this transaction and converts it to a
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* Transaction Layer Packet (TLP) message which is sent across the cDMI.
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*
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* 2. South Complex cDMI block receives this message and writes it to
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* the IPC-1 register block, causing an interrupt to the SCU
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*
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* 3. SCU firmware decodes this interrupt and IPC message and the appropriate
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* message handler is called within firmware.
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*/
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#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
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#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
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#define IPC_IOC 0x100 /* IPC command register IOC bit */
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struct intel_scu_ipc_dev {
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struct device dev;
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struct resource mem;
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struct module *owner;
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int irq;
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void __iomem *ipc_base;
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struct completion cmd_complete;
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};
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#define IPC_STATUS 0x04
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#define IPC_STATUS_IRQ BIT(2)
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#define IPC_STATUS_ERR BIT(1)
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#define IPC_STATUS_BUSY BIT(0)
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/*
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* IPC Write/Read Buffers:
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* 16 byte buffer for sending and receiving data to and from SCU.
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*/
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#define IPC_WRITE_BUFFER 0x80
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#define IPC_READ_BUFFER 0x90
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/* Timeout in jiffies */
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#define IPC_TIMEOUT (10 * HZ)
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static struct intel_scu_ipc_dev *ipcdev; /* Only one for now */
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static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
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static struct class intel_scu_ipc_class = {
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.name = "intel_scu_ipc",
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.owner = THIS_MODULE,
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};
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/**
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* intel_scu_ipc_dev_get() - Get SCU IPC instance
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*
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* The recommended new API takes SCU IPC instance as parameter and this
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* function can be called by driver to get the instance. This also makes
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* sure the driver providing the IPC functionality cannot be unloaded
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* while the caller has the instance.
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*
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* Call intel_scu_ipc_dev_put() to release the instance.
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*
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* Returns %NULL if SCU IPC is not currently available.
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*/
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struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void)
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{
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struct intel_scu_ipc_dev *scu = NULL;
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mutex_lock(&ipclock);
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if (ipcdev) {
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get_device(&ipcdev->dev);
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/*
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* Prevent the IPC provider from being unloaded while it
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* is being used.
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*/
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if (!try_module_get(ipcdev->owner))
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put_device(&ipcdev->dev);
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else
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scu = ipcdev;
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}
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mutex_unlock(&ipclock);
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return scu;
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}
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EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_get);
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/**
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* intel_scu_ipc_dev_put() - Put SCU IPC instance
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* @scu: SCU IPC instance
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*
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* This function releases the SCU IPC instance retrieved from
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* intel_scu_ipc_dev_get() and allows the driver providing IPC to be
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* unloaded.
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*/
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void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu)
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{
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if (scu) {
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module_put(scu->owner);
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put_device(&scu->dev);
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}
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}
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EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_put);
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struct intel_scu_ipc_devres {
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struct intel_scu_ipc_dev *scu;
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};
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static void devm_intel_scu_ipc_dev_release(struct device *dev, void *res)
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{
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struct intel_scu_ipc_devres *dr = res;
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struct intel_scu_ipc_dev *scu = dr->scu;
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intel_scu_ipc_dev_put(scu);
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}
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/**
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* devm_intel_scu_ipc_dev_get() - Allocate managed SCU IPC device
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* @dev: Device requesting the SCU IPC device
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*
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* The recommended new API takes SCU IPC instance as parameter and this
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* function can be called by driver to get the instance. This also makes
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* sure the driver providing the IPC functionality cannot be unloaded
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* while the caller has the instance.
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*
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* Returns %NULL if SCU IPC is not currently available.
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*/
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struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev)
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{
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struct intel_scu_ipc_devres *dr;
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struct intel_scu_ipc_dev *scu;
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dr = devres_alloc(devm_intel_scu_ipc_dev_release, sizeof(*dr), GFP_KERNEL);
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if (!dr)
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return NULL;
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scu = intel_scu_ipc_dev_get();
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if (!scu) {
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devres_free(dr);
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return NULL;
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}
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dr->scu = scu;
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devres_add(dev, dr);
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return scu;
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}
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EXPORT_SYMBOL_GPL(devm_intel_scu_ipc_dev_get);
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/*
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* Send ipc command
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* Command Register (Write Only):
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* A write to this register results in an interrupt to the SCU core processor
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* Format:
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* |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
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*/
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static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
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{
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reinit_completion(&scu->cmd_complete);
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writel(cmd | IPC_IOC, scu->ipc_base);
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}
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/*
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* Write ipc data
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* IPC Write Buffer (Write Only):
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* 16-byte buffer for sending data associated with IPC command to
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* SCU. Size of the data is specified in the IPC_COMMAND_REG register
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*/
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static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
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{
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writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset);
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}
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/*
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* Status Register (Read Only):
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* Driver will read this register to get the ready/busy status of the IPC
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* block and error status of the IPC command that was just processed by SCU
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* Format:
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* |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
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*/
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static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
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{
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return __raw_readl(scu->ipc_base + IPC_STATUS);
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}
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/* Read ipc byte data */
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static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
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{
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return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
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}
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/* Read ipc u32 data */
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static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
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{
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return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
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}
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/* Wait till scu status is busy */
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static inline int busy_loop(struct intel_scu_ipc_dev *scu)
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{
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unsigned long end = jiffies + IPC_TIMEOUT;
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do {
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u32 status;
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status = ipc_read_status(scu);
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if (!(status & IPC_STATUS_BUSY))
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return (status & IPC_STATUS_ERR) ? -EIO : 0;
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usleep_range(50, 100);
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} while (time_before(jiffies, end));
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return -ETIMEDOUT;
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}
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/* Wait till ipc ioc interrupt is received or timeout in 10 HZ */
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static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
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{
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int status;
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if (!wait_for_completion_timeout(&scu->cmd_complete, IPC_TIMEOUT))
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return -ETIMEDOUT;
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status = ipc_read_status(scu);
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if (status & IPC_STATUS_ERR)
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return -EIO;
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return 0;
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}
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static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
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{
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return scu->irq > 0 ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
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}
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/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
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static int pwr_reg_rdwr(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
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u32 count, u32 op, u32 id)
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{
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int nc;
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u32 offset = 0;
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int err;
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u8 cbuf[IPC_WWBUF_SIZE];
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u32 *wbuf = (u32 *)&cbuf;
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memset(cbuf, 0, sizeof(cbuf));
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mutex_lock(&ipclock);
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if (!scu)
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scu = ipcdev;
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if (!scu) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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for (nc = 0; nc < count; nc++, offset += 2) {
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cbuf[offset] = addr[nc];
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cbuf[offset + 1] = addr[nc] >> 8;
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}
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if (id == IPC_CMD_PCNTRL_R) {
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(scu, wbuf[nc], offset);
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ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_W) {
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for (nc = 0; nc < count; nc++, offset += 1)
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cbuf[offset] = data[nc];
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(scu, wbuf[nc], offset);
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ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_M) {
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cbuf[offset] = data[0];
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cbuf[offset + 1] = data[1];
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ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
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ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
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}
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err = intel_scu_ipc_check_status(scu);
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if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
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/* Workaround: values are read as 0 without memcpy_fromio */
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memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
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for (nc = 0; nc < count; nc++)
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data[nc] = ipc_data_readb(scu, nc);
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}
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mutex_unlock(&ipclock);
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return err;
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}
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/**
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* intel_scu_ipc_dev_ioread8() - Read a byte via the SCU
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* @scu: Optional SCU IPC instance
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* @addr: Register on SCU
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* @data: Return pointer for read byte
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*
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* Read a single register. Returns %0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr, u8 *data)
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{
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return pwr_reg_rdwr(scu, &addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_dev_ioread8);
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/**
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* intel_scu_ipc_dev_iowrite8() - Write a byte via the SCU
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* @scu: Optional SCU IPC instance
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* @addr: Register on SCU
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* @data: Byte to write
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*
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* Write a single register. Returns %0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr, u8 data)
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{
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return pwr_reg_rdwr(scu, &addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_dev_iowrite8);
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/**
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* intel_scu_ipc_dev_readv() - Read a set of registers
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* @scu: Optional SCU IPC instance
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* @addr: Register list
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* @data: Bytes to return
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* @len: Length of array
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*
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* Read registers. Returns %0 on success or an error code. All locking
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* between SCU accesses is handled for the caller.
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*
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* The largest array length permitted by the hardware is 5 items.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
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size_t len)
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{
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return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_dev_readv);
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/**
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* intel_scu_ipc_dev_writev() - Write a set of registers
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* @scu: Optional SCU IPC instance
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* @addr: Register list
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* @data: Bytes to write
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* @len: Length of array
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*
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* Write registers. Returns %0 on success or an error code. All locking
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* between SCU accesses is handled for the caller.
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*
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* The largest array length permitted by the hardware is 5 items.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
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size_t len)
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{
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return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_dev_writev);
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/**
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* intel_scu_ipc_dev_update() - Update a register
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* @scu: Optional SCU IPC instance
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* @addr: Register address
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* @data: Bits to update
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* @mask: Mask of bits to update
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*
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* Read-modify-write power control unit register. The first data argument
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* must be register value and second is mask value mask is a bitmap that
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* indicates which bits to update. %0 = masked. Don't modify this bit, %1 =
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* modify this bit. returns %0 on success or an error code.
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*
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* This function may sleep. Locking between SCU accesses is handled
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* for the caller.
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*/
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int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr, u8 data,
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u8 mask)
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{
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u8 tmp[2] = { data, mask };
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return pwr_reg_rdwr(scu, &addr, tmp, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
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}
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EXPORT_SYMBOL(intel_scu_ipc_dev_update);
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/**
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* intel_scu_ipc_dev_simple_command() - Send a simple command
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* @scu: Optional SCU IPC instance
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* @cmd: Command
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* @sub: Sub type
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*
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* Issue a simple command to the SCU. Do not use this interface if you must
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* then access data as any data values may be overwritten by another SCU
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* access by the time this function returns.
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*
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* This function may sleep. Locking for SCU accesses is handled for the
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* caller.
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*/
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int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,
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int sub)
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{
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u32 cmdval;
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int err;
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mutex_lock(&ipclock);
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if (!scu)
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scu = ipcdev;
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if (!scu) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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scu = ipcdev;
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cmdval = sub << 12 | cmd;
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ipc_command(scu, cmdval);
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err = intel_scu_ipc_check_status(scu);
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mutex_unlock(&ipclock);
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if (err)
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dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
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return err;
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}
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EXPORT_SYMBOL(intel_scu_ipc_dev_simple_command);
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/**
|
|
* intel_scu_ipc_dev_command_with_size() - Command with data
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* @scu: Optional SCU IPC instance
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* @cmd: Command
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* @sub: Sub type
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* @in: Input data
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|
* @inlen: Input length in bytes
|
|
* @size: Input size written to the IPC command register in whatever
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* units (dword, byte) the particular firmware requires. Normally
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|
* should be the same as @inlen.
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|
* @out: Output data
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|
* @outlen: Output length in bytes
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|
*
|
|
* Issue a command to the SCU which involves data transfers. Do the
|
|
* data copies under the lock but leave it for the caller to interpret.
|
|
*/
|
|
int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,
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int sub, const void *in, size_t inlen,
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size_t size, void *out, size_t outlen)
|
|
{
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|
size_t outbuflen = DIV_ROUND_UP(outlen, sizeof(u32));
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|
size_t inbuflen = DIV_ROUND_UP(inlen, sizeof(u32));
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|
u32 cmdval, inbuf[4] = {};
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int i, err;
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|
|
|
if (inbuflen > 4 || outbuflen > 4)
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return -EINVAL;
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|
|
|
mutex_lock(&ipclock);
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|
if (!scu)
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scu = ipcdev;
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|
if (!scu) {
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|
mutex_unlock(&ipclock);
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|
return -ENODEV;
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}
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|
|
|
memcpy(inbuf, in, inlen);
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for (i = 0; i < inbuflen; i++)
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ipc_data_writel(scu, inbuf[i], 4 * i);
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cmdval = (size << 16) | (sub << 12) | cmd;
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ipc_command(scu, cmdval);
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err = intel_scu_ipc_check_status(scu);
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|
|
|
if (!err) {
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|
u32 outbuf[4] = {};
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|
|
|
for (i = 0; i < outbuflen; i++)
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|
outbuf[i] = ipc_data_readl(scu, 4 * i);
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|
|
|
memcpy(out, outbuf, outlen);
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|
}
|
|
|
|
mutex_unlock(&ipclock);
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if (err)
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dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
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|
return err;
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|
}
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|
EXPORT_SYMBOL(intel_scu_ipc_dev_command_with_size);
|
|
|
|
/*
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|
* Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
|
|
* When ioc bit is set to 1, caller api must wait for interrupt handler called
|
|
* which in turn unlocks the caller api. Currently this is not used
|
|
*
|
|
* This is edge triggered so we need take no action to clear anything
|
|
*/
|
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static irqreturn_t ioc(int irq, void *dev_id)
|
|
{
|
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struct intel_scu_ipc_dev *scu = dev_id;
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int status = ipc_read_status(scu);
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|
|
|
writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS);
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complete(&scu->cmd_complete);
|
|
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|
return IRQ_HANDLED;
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|
}
|
|
|
|
static void intel_scu_ipc_release(struct device *dev)
|
|
{
|
|
struct intel_scu_ipc_dev *scu;
|
|
|
|
scu = container_of(dev, struct intel_scu_ipc_dev, dev);
|
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if (scu->irq > 0)
|
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free_irq(scu->irq, scu);
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iounmap(scu->ipc_base);
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|
release_mem_region(scu->mem.start, resource_size(&scu->mem));
|
|
kfree(scu);
|
|
}
|
|
|
|
/**
|
|
* __intel_scu_ipc_register() - Register SCU IPC device
|
|
* @parent: Parent device
|
|
* @scu_data: Data used to configure SCU IPC
|
|
* @owner: Module registering the SCU IPC device
|
|
*
|
|
* Call this function to register SCU IPC mechanism under @parent.
|
|
* Returns pointer to the new SCU IPC device or ERR_PTR() in case of
|
|
* failure. The caller may use the returned instance if it needs to do
|
|
* SCU IPC calls itself.
|
|
*/
|
|
struct intel_scu_ipc_dev *
|
|
__intel_scu_ipc_register(struct device *parent,
|
|
const struct intel_scu_ipc_data *scu_data,
|
|
struct module *owner)
|
|
{
|
|
int err;
|
|
struct intel_scu_ipc_dev *scu;
|
|
void __iomem *ipc_base;
|
|
|
|
mutex_lock(&ipclock);
|
|
/* We support only one IPC */
|
|
if (ipcdev) {
|
|
err = -EBUSY;
|
|
goto err_unlock;
|
|
}
|
|
|
|
scu = kzalloc(sizeof(*scu), GFP_KERNEL);
|
|
if (!scu) {
|
|
err = -ENOMEM;
|
|
goto err_unlock;
|
|
}
|
|
|
|
scu->owner = owner;
|
|
scu->dev.parent = parent;
|
|
scu->dev.class = &intel_scu_ipc_class;
|
|
scu->dev.release = intel_scu_ipc_release;
|
|
dev_set_name(&scu->dev, "intel_scu_ipc");
|
|
|
|
if (!request_mem_region(scu_data->mem.start, resource_size(&scu_data->mem),
|
|
"intel_scu_ipc")) {
|
|
err = -EBUSY;
|
|
goto err_free;
|
|
}
|
|
|
|
ipc_base = ioremap(scu_data->mem.start, resource_size(&scu_data->mem));
|
|
if (!ipc_base) {
|
|
err = -ENOMEM;
|
|
goto err_release;
|
|
}
|
|
|
|
scu->ipc_base = ipc_base;
|
|
scu->mem = scu_data->mem;
|
|
scu->irq = scu_data->irq;
|
|
init_completion(&scu->cmd_complete);
|
|
|
|
if (scu->irq > 0) {
|
|
err = request_irq(scu->irq, ioc, 0, "intel_scu_ipc", scu);
|
|
if (err)
|
|
goto err_unmap;
|
|
}
|
|
|
|
/*
|
|
* After this point intel_scu_ipc_release() takes care of
|
|
* releasing the SCU IPC resources once refcount drops to zero.
|
|
*/
|
|
err = device_register(&scu->dev);
|
|
if (err) {
|
|
put_device(&scu->dev);
|
|
goto err_unlock;
|
|
}
|
|
|
|
/* Assign device at last */
|
|
ipcdev = scu;
|
|
mutex_unlock(&ipclock);
|
|
|
|
return scu;
|
|
|
|
err_unmap:
|
|
iounmap(ipc_base);
|
|
err_release:
|
|
release_mem_region(scu_data->mem.start, resource_size(&scu_data->mem));
|
|
err_free:
|
|
kfree(scu);
|
|
err_unlock:
|
|
mutex_unlock(&ipclock);
|
|
|
|
return ERR_PTR(err);
|
|
}
|
|
EXPORT_SYMBOL_GPL(__intel_scu_ipc_register);
|
|
|
|
/**
|
|
* intel_scu_ipc_unregister() - Unregister SCU IPC
|
|
* @scu: SCU IPC handle
|
|
*
|
|
* This unregisters the SCU IPC device and releases the acquired
|
|
* resources once the refcount goes to zero.
|
|
*/
|
|
void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu)
|
|
{
|
|
mutex_lock(&ipclock);
|
|
if (!WARN_ON(!ipcdev)) {
|
|
ipcdev = NULL;
|
|
device_unregister(&scu->dev);
|
|
}
|
|
mutex_unlock(&ipclock);
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_scu_ipc_unregister);
|
|
|
|
static void devm_intel_scu_ipc_unregister(struct device *dev, void *res)
|
|
{
|
|
struct intel_scu_ipc_devres *dr = res;
|
|
struct intel_scu_ipc_dev *scu = dr->scu;
|
|
|
|
intel_scu_ipc_unregister(scu);
|
|
}
|
|
|
|
/**
|
|
* __devm_intel_scu_ipc_register() - Register managed SCU IPC device
|
|
* @parent: Parent device
|
|
* @scu_data: Data used to configure SCU IPC
|
|
* @owner: Module registering the SCU IPC device
|
|
*
|
|
* Call this function to register managed SCU IPC mechanism under
|
|
* @parent. Returns pointer to the new SCU IPC device or ERR_PTR() in
|
|
* case of failure. The caller may use the returned instance if it needs
|
|
* to do SCU IPC calls itself.
|
|
*/
|
|
struct intel_scu_ipc_dev *
|
|
__devm_intel_scu_ipc_register(struct device *parent,
|
|
const struct intel_scu_ipc_data *scu_data,
|
|
struct module *owner)
|
|
{
|
|
struct intel_scu_ipc_devres *dr;
|
|
struct intel_scu_ipc_dev *scu;
|
|
|
|
dr = devres_alloc(devm_intel_scu_ipc_unregister, sizeof(*dr), GFP_KERNEL);
|
|
if (!dr)
|
|
return NULL;
|
|
|
|
scu = __intel_scu_ipc_register(parent, scu_data, owner);
|
|
if (IS_ERR(scu)) {
|
|
devres_free(dr);
|
|
return scu;
|
|
}
|
|
|
|
dr->scu = scu;
|
|
devres_add(parent, dr);
|
|
|
|
return scu;
|
|
}
|
|
EXPORT_SYMBOL_GPL(__devm_intel_scu_ipc_register);
|
|
|
|
static int __init intel_scu_ipc_init(void)
|
|
{
|
|
return class_register(&intel_scu_ipc_class);
|
|
}
|
|
subsys_initcall(intel_scu_ipc_init);
|
|
|
|
static void __exit intel_scu_ipc_exit(void)
|
|
{
|
|
class_unregister(&intel_scu_ipc_class);
|
|
}
|
|
module_exit(intel_scu_ipc_exit);
|