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fef6e24c8b
SDMA (System DMA) is a general purpose DMA engine usable
by UMDs for transfers or the kernel for paging or GPUVM
updates.
v1: support basic funcitonalites includes rb, ib, vm,
copy buffer and trap irq
v2: convert to use new get_vm_pde in emit_vm_flush
v3: retire amdgpu_ttm_set_active_vram_size from sdma v5
v4: retire the redundant hdp_invalidate implementation
v5: squash in updates
v6: some golden regs moved to vbios
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
45 lines
1.8 KiB
C
45 lines
1.8 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SDMA_V5_0_H__
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#define __SDMA_V5_0_H__
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enum sdma_v5_0_utcl2_cache_read_policy {
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CACHE_READ_POLICY_L2__LRU = 0x00000000,
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CACHE_READ_POLICY_L2__STREAM = 0x00000001,
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CACHE_READ_POLICY_L2__NOA = 0x00000002,
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CACHE_READ_POLICY_L2__DEFAULT = CACHE_READ_POLICY_L2__NOA,
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};
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enum sdma_v5_0_utcl2_cache_write_policy {
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CACHE_WRITE_POLICY_L2__LRU = 0x00000000,
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CACHE_WRITE_POLICY_L2__STREAM = 0x00000001,
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CACHE_WRITE_POLICY_L2__NOA = 0x00000002,
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CACHE_WRITE_POLICY_L2__BYPASS = 0x00000003,
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CACHE_WRITE_POLICY_L2__DEFAULT = CACHE_WRITE_POLICY_L2__BYPASS,
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};
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extern const struct amd_ip_funcs sdma_v5_0_ip_funcs;
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extern const struct amdgpu_ip_block_version sdma_v5_0_ip_block;
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#endif /* __SDMA_V5_0_H__ */
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