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![Joonyoung Shim](/assets/img/avatar_default.png)
Changelog v3: - use __u64 instead of pointer in ioctl struct. The G2D is a 2D graphic accelerator that supports Bit Block Transfer. This G2D driver is exynos drm specific and supports only G2D(version 4.1) of later Exynos series from Exynos4X12 because supporting DMA. The G2D is performed by two tasks simply. 1. Configures the rendering parameters, such as foreground color and coordinates data by setting the drawing context registers. 2. Start the rendering process by setting thre relevant command registers accordingly. The G2D version 4.1 supports DMA mode as host interface. User can make command list to reduce HOST(ARM) loads. The contents of The command list is setted to relevant registers of G2D by DMA. The command list is composed Header and command sets and Tail. - Header: The number of command set(4Bytes) - Command set: Register offset(4Bytes) + Register data(4Bytes) - Tail: Pointer of base address of the other command list(4Bytes) By Tail field, the G2D can process many command lists without halt at one go. The G2D has following the rendering pipeline. --> Primitive Drawing --> Rotation --> Clipping --> Bilinear Sampling --> Color Key --> ROP --> Mask Operation --> Alpha Blending --> Dithering --> FrameBuffer And supports various operations from the rendering pipeline. - copy - fast solid color fill - window clipping - rotation - flip - 4 operand raster operation(ROP4) - masking operation - alpha blending - color key - dithering - etc User should make the command list to data and registers needed by operation to use. The Exynos G2D driver only manages the command lists received from user. Some registers needs memory base address(physical address) of image. User doesn't know its physical address, so fills the gem handle of that memory than address to command sets, then G2D driver converts it to memory base address. We adds three ioctls and one event for Exynos G2D. - ioctls DRM_EXYNOS_G2D_GET_VER: get the G2D hardware version DRM_EXYNOS_G2D_SET_CMDLIST: set the command list from user to driver DRM_EXYNOS_G2D_EXEC: execute the command lists setted to driver - event DRM_EXYNOS_G2D_EVENT: event to give notification completion of the command list to user Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
268 lines
7.4 KiB
C
268 lines
7.4 KiB
C
/* exynos_drm.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Authors:
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* Inki Dae <inki.dae@samsung.com>
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* Joonyoung Shim <jy0922.shim@samsung.com>
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* Seung-Woo Kim <sw0312.kim@samsung.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _EXYNOS_DRM_H_
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#define _EXYNOS_DRM_H_
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#include "drm.h"
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/**
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* User-desired buffer creation information structure.
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*
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* @size: user-desired memory allocation size.
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* - this size value would be page-aligned internally.
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* @flags: user request for setting memory type or cache attributes.
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* @handle: returned a handle to created gem object.
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* - this handle will be set by gem module of kernel side.
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*/
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struct drm_exynos_gem_create {
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uint64_t size;
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unsigned int flags;
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unsigned int handle;
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};
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/**
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* A structure for getting buffer offset.
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*
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* @handle: a pointer to gem object created.
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* @pad: just padding to be 64-bit aligned.
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* @offset: relatived offset value of the memory region allocated.
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* - this value should be set by user.
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*/
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struct drm_exynos_gem_map_off {
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unsigned int handle;
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unsigned int pad;
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uint64_t offset;
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};
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/**
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* A structure for mapping buffer.
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*
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* @handle: a handle to gem object created.
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* @size: memory size to be mapped.
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* @mapped: having user virtual address mmaped.
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* - this variable would be filled by exynos gem module
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* of kernel side with user virtual address which is allocated
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* by do_mmap().
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*/
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struct drm_exynos_gem_mmap {
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unsigned int handle;
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unsigned int size;
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uint64_t mapped;
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};
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/**
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* A structure to gem information.
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*
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* @handle: a handle to gem object created.
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* @flags: flag value including memory type and cache attribute and
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* this value would be set by driver.
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* @size: size to memory region allocated by gem and this size would
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* be set by driver.
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*/
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struct drm_exynos_gem_info {
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unsigned int handle;
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unsigned int flags;
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uint64_t size;
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};
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/**
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* A structure for user connection request of virtual display.
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*
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* @connection: indicate whether doing connetion or not by user.
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* @extensions: if this value is 1 then the vidi driver would need additional
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* 128bytes edid data.
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* @edid: the edid data pointer from user side.
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*/
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struct drm_exynos_vidi_connection {
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unsigned int connection;
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unsigned int extensions;
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uint64_t edid;
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};
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struct drm_exynos_plane_set_zpos {
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__u32 plane_id;
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__s32 zpos;
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};
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/* memory type definitions. */
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enum e_drm_exynos_gem_mem_type {
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/* Physically Continuous memory and used as default. */
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EXYNOS_BO_CONTIG = 0 << 0,
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/* Physically Non-Continuous memory. */
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EXYNOS_BO_NONCONTIG = 1 << 0,
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/* non-cachable mapping and used as default. */
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EXYNOS_BO_NONCACHABLE = 0 << 1,
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/* cachable mapping. */
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EXYNOS_BO_CACHABLE = 1 << 1,
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/* write-combine mapping. */
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EXYNOS_BO_WC = 1 << 2,
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EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
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EXYNOS_BO_WC
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};
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struct drm_exynos_g2d_get_ver {
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__u32 major;
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__u32 minor;
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};
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struct drm_exynos_g2d_cmd {
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__u32 offset;
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__u32 data;
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};
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enum drm_exynos_g2d_event_type {
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G2D_EVENT_NOT,
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G2D_EVENT_NONSTOP,
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G2D_EVENT_STOP, /* not yet */
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};
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struct drm_exynos_g2d_set_cmdlist {
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__u64 cmd;
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__u64 cmd_gem;
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__u32 cmd_nr;
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__u32 cmd_gem_nr;
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/* for g2d event */
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__u64 event_type;
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__u64 user_data;
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};
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struct drm_exynos_g2d_exec {
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__u64 async;
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};
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#define DRM_EXYNOS_GEM_CREATE 0x00
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#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
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#define DRM_EXYNOS_GEM_MMAP 0x02
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/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
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#define DRM_EXYNOS_GEM_GET 0x04
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#define DRM_EXYNOS_PLANE_SET_ZPOS 0x06
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#define DRM_EXYNOS_VIDI_CONNECTION 0x07
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/* G2D */
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#define DRM_EXYNOS_G2D_GET_VER 0x20
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#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
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#define DRM_EXYNOS_G2D_EXEC 0x22
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#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
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#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off)
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#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
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#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
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#define DRM_IOCTL_EXYNOS_PLANE_SET_ZPOS DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_PLANE_SET_ZPOS, struct drm_exynos_plane_set_zpos)
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#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
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#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
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#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
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#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
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/* EXYNOS specific events */
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#define DRM_EXYNOS_G2D_EVENT 0x80000000
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struct drm_exynos_g2d_event {
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struct drm_event base;
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__u64 user_data;
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__u32 tv_sec;
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__u32 tv_usec;
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__u32 cmdlist_no;
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__u32 reserved;
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};
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#ifdef __KERNEL__
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/**
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* A structure for lcd panel information.
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*
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* @timing: default video mode for initializing
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* @width_mm: physical size of lcd width.
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* @height_mm: physical size of lcd height.
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*/
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struct exynos_drm_panel_info {
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struct fb_videomode timing;
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u32 width_mm;
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u32 height_mm;
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};
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/**
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* Platform Specific Structure for DRM based FIMD.
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*
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* @panel: default panel info for initializing
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* @default_win: default window layer number to be used for UI.
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* @bpp: default bit per pixel.
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*/
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struct exynos_drm_fimd_pdata {
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struct exynos_drm_panel_info panel;
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u32 vidcon0;
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u32 vidcon1;
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unsigned int default_win;
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unsigned int bpp;
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};
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/**
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* Platform Specific Structure for DRM based HDMI.
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*
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* @hdmi_dev: device point to specific hdmi driver.
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* @mixer_dev: device point to specific mixer driver.
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*
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* this structure is used for common hdmi driver and each device object
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* would be used to access specific device driver(hdmi or mixer driver)
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*/
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struct exynos_drm_common_hdmi_pd {
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struct device *hdmi_dev;
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struct device *mixer_dev;
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};
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/**
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* Platform Specific Structure for DRM based HDMI core.
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*
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* @is_v13: set if hdmi version 13 is.
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* @cfg_hpd: function pointer to configure hdmi hotplug detection pin
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* @get_hpd: function pointer to get value of hdmi hotplug detection pin
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*/
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struct exynos_drm_hdmi_pdata {
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bool is_v13;
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void (*cfg_hpd)(bool external);
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int (*get_hpd)(void);
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};
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#endif /* __KERNEL__ */
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#endif /* _EXYNOS_DRM_H_ */
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