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The MT8167 SoC provides the following peripherals: GPIO, UART, USB2, SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, TImers, IR, Ethernet, Audio (I2S, SPDIF, TDM, HDMI), HDMI, DSI, CSI, MDP (Multimedia Data Path), Video encoding (H.264), Video Decoding (H.264, VP8). The MT8167 is compatible with MT8516 but provides multimedia IPs to it. This commit is just adding the basic dtsi file with the support of the following IOs: GPIO, Clocks. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20201027194816.1227654-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
61 lines
1.4 KiB
Text
61 lines
1.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Copyright (c) 2020 BayLibre, SAS.
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* Author: Fabien Parent <fparent@baylibre.com>
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*/
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#include <dt-bindings/clock/mt8167-clk.h>
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#include <dt-bindings/memory/mt8167-larb-port.h>
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#include "mt8167-pinfunc.h"
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#include "mt8516.dtsi"
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/ {
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compatible = "mediatek,mt8167";
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soc {
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topckgen: topckgen@10000000 {
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compatible = "mediatek,mt8167-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: infracfg@10001000 {
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compatible = "mediatek,mt8167-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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apmixedsys: apmixedsys@10018000 {
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compatible = "mediatek,mt8167-apmixedsys", "syscon";
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reg = <0 0x10018000 0 0x710>;
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#clock-cells = <1>;
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};
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt8167-imgsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt8167-vdecsys", "syscon";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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pio: pinctrl@1000b000 {
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compatible = "mediatek,mt8167-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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