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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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7c50136a8a
Avoid excessive scheduling delays under a preemptible kernel by yielding the NEON after every block of input. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
491 lines
10 KiB
ArmAsm
491 lines
10 KiB
ArmAsm
/*
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* Accelerated GHASH implementation with ARMv8 PMULL instructions.
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*
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* Copyright (C) 2014 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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SHASH .req v0
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SHASH2 .req v1
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T1 .req v2
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T2 .req v3
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MASK .req v4
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XL .req v5
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XM .req v6
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XH .req v7
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IN1 .req v7
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k00_16 .req v8
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k32_48 .req v9
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t3 .req v10
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t4 .req v11
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t5 .req v12
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t6 .req v13
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t7 .req v14
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t8 .req v15
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t9 .req v16
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perm1 .req v17
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perm2 .req v18
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perm3 .req v19
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sh1 .req v20
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sh2 .req v21
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sh3 .req v22
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sh4 .req v23
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ss1 .req v24
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ss2 .req v25
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ss3 .req v26
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ss4 .req v27
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.text
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.arch armv8-a+crypto
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.macro __pmull_p64, rd, rn, rm
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pmull \rd\().1q, \rn\().1d, \rm\().1d
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.endm
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.macro __pmull2_p64, rd, rn, rm
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pmull2 \rd\().1q, \rn\().2d, \rm\().2d
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.endm
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.macro __pmull_p8, rq, ad, bd
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ext t3.8b, \ad\().8b, \ad\().8b, #1 // A1
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ext t5.8b, \ad\().8b, \ad\().8b, #2 // A2
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ext t7.8b, \ad\().8b, \ad\().8b, #3 // A3
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__pmull_p8_\bd \rq, \ad
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.endm
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.macro __pmull2_p8, rq, ad, bd
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tbl t3.16b, {\ad\().16b}, perm1.16b // A1
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tbl t5.16b, {\ad\().16b}, perm2.16b // A2
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tbl t7.16b, {\ad\().16b}, perm3.16b // A3
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__pmull2_p8_\bd \rq, \ad
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.endm
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.macro __pmull_p8_SHASH, rq, ad
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__pmull_p8_tail \rq, \ad\().8b, SHASH.8b, 8b,, sh1, sh2, sh3, sh4
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.endm
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.macro __pmull_p8_SHASH2, rq, ad
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__pmull_p8_tail \rq, \ad\().8b, SHASH2.8b, 8b,, ss1, ss2, ss3, ss4
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.endm
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.macro __pmull2_p8_SHASH, rq, ad
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__pmull_p8_tail \rq, \ad\().16b, SHASH.16b, 16b, 2, sh1, sh2, sh3, sh4
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.endm
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.macro __pmull_p8_tail, rq, ad, bd, nb, t, b1, b2, b3, b4
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pmull\t t3.8h, t3.\nb, \bd // F = A1*B
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pmull\t t4.8h, \ad, \b1\().\nb // E = A*B1
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pmull\t t5.8h, t5.\nb, \bd // H = A2*B
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pmull\t t6.8h, \ad, \b2\().\nb // G = A*B2
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pmull\t t7.8h, t7.\nb, \bd // J = A3*B
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pmull\t t8.8h, \ad, \b3\().\nb // I = A*B3
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pmull\t t9.8h, \ad, \b4\().\nb // K = A*B4
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pmull\t \rq\().8h, \ad, \bd // D = A*B
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eor t3.16b, t3.16b, t4.16b // L = E + F
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eor t5.16b, t5.16b, t6.16b // M = G + H
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eor t7.16b, t7.16b, t8.16b // N = I + J
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uzp1 t4.2d, t3.2d, t5.2d
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uzp2 t3.2d, t3.2d, t5.2d
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uzp1 t6.2d, t7.2d, t9.2d
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uzp2 t7.2d, t7.2d, t9.2d
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// t3 = (L) (P0 + P1) << 8
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// t5 = (M) (P2 + P3) << 16
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eor t4.16b, t4.16b, t3.16b
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and t3.16b, t3.16b, k32_48.16b
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// t7 = (N) (P4 + P5) << 24
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// t9 = (K) (P6 + P7) << 32
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eor t6.16b, t6.16b, t7.16b
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and t7.16b, t7.16b, k00_16.16b
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eor t4.16b, t4.16b, t3.16b
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eor t6.16b, t6.16b, t7.16b
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zip2 t5.2d, t4.2d, t3.2d
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zip1 t3.2d, t4.2d, t3.2d
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zip2 t9.2d, t6.2d, t7.2d
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zip1 t7.2d, t6.2d, t7.2d
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ext t3.16b, t3.16b, t3.16b, #15
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ext t5.16b, t5.16b, t5.16b, #14
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ext t7.16b, t7.16b, t7.16b, #13
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ext t9.16b, t9.16b, t9.16b, #12
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eor t3.16b, t3.16b, t5.16b
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eor t7.16b, t7.16b, t9.16b
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eor \rq\().16b, \rq\().16b, t3.16b
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eor \rq\().16b, \rq\().16b, t7.16b
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.endm
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.macro __pmull_pre_p64
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movi MASK.16b, #0xe1
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shl MASK.2d, MASK.2d, #57
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.endm
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.macro __pmull_pre_p8
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// k00_16 := 0x0000000000000000_000000000000ffff
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// k32_48 := 0x00000000ffffffff_0000ffffffffffff
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movi k32_48.2d, #0xffffffff
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mov k32_48.h[2], k32_48.h[0]
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ushr k00_16.2d, k32_48.2d, #32
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// prepare the permutation vectors
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mov_q x5, 0x080f0e0d0c0b0a09
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movi T1.8b, #8
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dup perm1.2d, x5
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eor perm1.16b, perm1.16b, T1.16b
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ushr perm2.2d, perm1.2d, #8
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ushr perm3.2d, perm1.2d, #16
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ushr T1.2d, perm1.2d, #24
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sli perm2.2d, perm1.2d, #56
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sli perm3.2d, perm1.2d, #48
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sli T1.2d, perm1.2d, #40
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// precompute loop invariants
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tbl sh1.16b, {SHASH.16b}, perm1.16b
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tbl sh2.16b, {SHASH.16b}, perm2.16b
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tbl sh3.16b, {SHASH.16b}, perm3.16b
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tbl sh4.16b, {SHASH.16b}, T1.16b
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ext ss1.8b, SHASH2.8b, SHASH2.8b, #1
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ext ss2.8b, SHASH2.8b, SHASH2.8b, #2
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ext ss3.8b, SHASH2.8b, SHASH2.8b, #3
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ext ss4.8b, SHASH2.8b, SHASH2.8b, #4
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.endm
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//
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// PMULL (64x64->128) based reduction for CPUs that can do
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// it in a single instruction.
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//
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.macro __pmull_reduce_p64
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pmull T2.1q, XL.1d, MASK.1d
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eor XM.16b, XM.16b, T1.16b
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mov XH.d[0], XM.d[1]
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mov XM.d[1], XL.d[0]
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eor XL.16b, XM.16b, T2.16b
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ext T2.16b, XL.16b, XL.16b, #8
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pmull XL.1q, XL.1d, MASK.1d
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.endm
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//
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// Alternative reduction for CPUs that lack support for the
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// 64x64->128 PMULL instruction
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//
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.macro __pmull_reduce_p8
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eor XM.16b, XM.16b, T1.16b
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mov XL.d[1], XM.d[0]
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mov XH.d[0], XM.d[1]
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shl T1.2d, XL.2d, #57
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shl T2.2d, XL.2d, #62
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eor T2.16b, T2.16b, T1.16b
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shl T1.2d, XL.2d, #63
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eor T2.16b, T2.16b, T1.16b
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ext T1.16b, XL.16b, XH.16b, #8
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eor T2.16b, T2.16b, T1.16b
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mov XL.d[1], T2.d[0]
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mov XH.d[0], T2.d[1]
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ushr T2.2d, XL.2d, #1
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eor XH.16b, XH.16b, XL.16b
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eor XL.16b, XL.16b, T2.16b
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ushr T2.2d, T2.2d, #6
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ushr XL.2d, XL.2d, #1
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.endm
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.macro __pmull_ghash, pn
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frame_push 5
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mov x19, x0
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mov x20, x1
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mov x21, x2
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mov x22, x3
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mov x23, x4
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0: ld1 {SHASH.2d}, [x22]
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ld1 {XL.2d}, [x20]
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ext SHASH2.16b, SHASH.16b, SHASH.16b, #8
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eor SHASH2.16b, SHASH2.16b, SHASH.16b
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__pmull_pre_\pn
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/* do the head block first, if supplied */
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cbz x23, 1f
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ld1 {T1.2d}, [x23]
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mov x23, xzr
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b 2f
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1: ld1 {T1.2d}, [x21], #16
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sub w19, w19, #1
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2: /* multiply XL by SHASH in GF(2^128) */
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CPU_LE( rev64 T1.16b, T1.16b )
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ext T2.16b, XL.16b, XL.16b, #8
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ext IN1.16b, T1.16b, T1.16b, #8
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eor T1.16b, T1.16b, T2.16b
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eor XL.16b, XL.16b, IN1.16b
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__pmull2_\pn XH, XL, SHASH // a1 * b1
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eor T1.16b, T1.16b, XL.16b
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__pmull_\pn XL, XL, SHASH // a0 * b0
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__pmull_\pn XM, T1, SHASH2 // (a1 + a0)(b1 + b0)
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eor T2.16b, XL.16b, XH.16b
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ext T1.16b, XL.16b, XH.16b, #8
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eor XM.16b, XM.16b, T2.16b
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__pmull_reduce_\pn
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eor T2.16b, T2.16b, XH.16b
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eor XL.16b, XL.16b, T2.16b
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cbz w19, 3f
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if_will_cond_yield_neon
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st1 {XL.2d}, [x20]
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do_cond_yield_neon
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b 0b
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endif_yield_neon
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b 1b
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3: st1 {XL.2d}, [x20]
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frame_pop
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ret
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.endm
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/*
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* void pmull_ghash_update(int blocks, u64 dg[], const char *src,
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* struct ghash_key const *k, const char *head)
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*/
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ENTRY(pmull_ghash_update_p64)
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__pmull_ghash p64
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ENDPROC(pmull_ghash_update_p64)
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ENTRY(pmull_ghash_update_p8)
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__pmull_ghash p8
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ENDPROC(pmull_ghash_update_p8)
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KS .req v8
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CTR .req v9
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INP .req v10
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.macro load_round_keys, rounds, rk
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cmp \rounds, #12
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blo 2222f /* 128 bits */
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beq 1111f /* 192 bits */
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ld1 {v17.4s-v18.4s}, [\rk], #32
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1111: ld1 {v19.4s-v20.4s}, [\rk], #32
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2222: ld1 {v21.4s-v24.4s}, [\rk], #64
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ld1 {v25.4s-v28.4s}, [\rk], #64
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ld1 {v29.4s-v31.4s}, [\rk]
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.endm
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.macro enc_round, state, key
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aese \state\().16b, \key\().16b
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aesmc \state\().16b, \state\().16b
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.endm
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.macro enc_block, state, rounds
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cmp \rounds, #12
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b.lo 2222f /* 128 bits */
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b.eq 1111f /* 192 bits */
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enc_round \state, v17
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enc_round \state, v18
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1111: enc_round \state, v19
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enc_round \state, v20
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2222: .irp key, v21, v22, v23, v24, v25, v26, v27, v28, v29
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enc_round \state, \key
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.endr
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aese \state\().16b, v30.16b
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eor \state\().16b, \state\().16b, v31.16b
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.endm
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.macro pmull_gcm_do_crypt, enc
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frame_push 10
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mov x19, x0
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mov x20, x1
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mov x21, x2
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mov x22, x3
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mov x23, x4
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mov x24, x5
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mov x25, x6
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mov x26, x7
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.if \enc == 1
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ldr x27, [sp, #96] // first stacked arg
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.endif
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ldr x28, [x24, #8] // load lower counter
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CPU_LE( rev x28, x28 )
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0: mov x0, x25
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load_round_keys w26, x0
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ld1 {SHASH.2d}, [x23]
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ld1 {XL.2d}, [x20]
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movi MASK.16b, #0xe1
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ext SHASH2.16b, SHASH.16b, SHASH.16b, #8
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shl MASK.2d, MASK.2d, #57
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eor SHASH2.16b, SHASH2.16b, SHASH.16b
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.if \enc == 1
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ld1 {KS.16b}, [x27]
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.endif
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1: ld1 {CTR.8b}, [x24] // load upper counter
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ld1 {INP.16b}, [x22], #16
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rev x9, x28
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add x28, x28, #1
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sub w19, w19, #1
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ins CTR.d[1], x9 // set lower counter
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.if \enc == 1
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eor INP.16b, INP.16b, KS.16b // encrypt input
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st1 {INP.16b}, [x21], #16
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.endif
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rev64 T1.16b, INP.16b
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cmp w26, #12
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b.ge 4f // AES-192/256?
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2: enc_round CTR, v21
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ext T2.16b, XL.16b, XL.16b, #8
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ext IN1.16b, T1.16b, T1.16b, #8
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enc_round CTR, v22
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eor T1.16b, T1.16b, T2.16b
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eor XL.16b, XL.16b, IN1.16b
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enc_round CTR, v23
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pmull2 XH.1q, SHASH.2d, XL.2d // a1 * b1
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eor T1.16b, T1.16b, XL.16b
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enc_round CTR, v24
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pmull XL.1q, SHASH.1d, XL.1d // a0 * b0
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pmull XM.1q, SHASH2.1d, T1.1d // (a1 + a0)(b1 + b0)
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enc_round CTR, v25
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ext T1.16b, XL.16b, XH.16b, #8
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eor T2.16b, XL.16b, XH.16b
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eor XM.16b, XM.16b, T1.16b
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enc_round CTR, v26
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eor XM.16b, XM.16b, T2.16b
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pmull T2.1q, XL.1d, MASK.1d
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enc_round CTR, v27
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mov XH.d[0], XM.d[1]
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mov XM.d[1], XL.d[0]
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enc_round CTR, v28
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eor XL.16b, XM.16b, T2.16b
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enc_round CTR, v29
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ext T2.16b, XL.16b, XL.16b, #8
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aese CTR.16b, v30.16b
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pmull XL.1q, XL.1d, MASK.1d
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eor T2.16b, T2.16b, XH.16b
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eor KS.16b, CTR.16b, v31.16b
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eor XL.16b, XL.16b, T2.16b
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.if \enc == 0
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eor INP.16b, INP.16b, KS.16b
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st1 {INP.16b}, [x21], #16
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.endif
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cbz w19, 3f
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if_will_cond_yield_neon
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st1 {XL.2d}, [x20]
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.if \enc == 1
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st1 {KS.16b}, [x27]
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.endif
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do_cond_yield_neon
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b 0b
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endif_yield_neon
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b 1b
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3: st1 {XL.2d}, [x20]
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.if \enc == 1
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st1 {KS.16b}, [x27]
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.endif
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CPU_LE( rev x28, x28 )
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str x28, [x24, #8] // store lower counter
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frame_pop
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ret
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4: b.eq 5f // AES-192?
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enc_round CTR, v17
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enc_round CTR, v18
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5: enc_round CTR, v19
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enc_round CTR, v20
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b 2b
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.endm
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/*
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* void pmull_gcm_encrypt(int blocks, u64 dg[], u8 dst[], const u8 src[],
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* struct ghash_key const *k, u8 ctr[],
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* int rounds, u8 ks[])
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*/
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ENTRY(pmull_gcm_encrypt)
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pmull_gcm_do_crypt 1
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ENDPROC(pmull_gcm_encrypt)
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/*
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* void pmull_gcm_decrypt(int blocks, u64 dg[], u8 dst[], const u8 src[],
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* struct ghash_key const *k, u8 ctr[],
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* int rounds)
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*/
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ENTRY(pmull_gcm_decrypt)
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pmull_gcm_do_crypt 0
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ENDPROC(pmull_gcm_decrypt)
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/*
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* void pmull_gcm_encrypt_block(u8 dst[], u8 src[], u8 rk[], int rounds)
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*/
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ENTRY(pmull_gcm_encrypt_block)
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cbz x2, 0f
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load_round_keys w3, x2
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0: ld1 {v0.16b}, [x1]
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enc_block v0, w3
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st1 {v0.16b}, [x0]
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ret
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ENDPROC(pmull_gcm_encrypt_block)
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