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463f46e114
This branch has three new iommufd capabilities:
- Dirty tracking for DMA. AMD/ARM/Intel CPUs can now record if a DMA
writes to a page in the IOPTEs within the IO page table. This can be used
to generate a record of what memory is being dirtied by DMA activities
during a VM migration process. A VMM like qemu will combine the IOMMU
dirty bits with the CPU's dirty log to determine what memory to
transfer.
VFIO already has a DMA dirty tracking framework that requires PCI
devices to implement tracking HW internally. The iommufd version
provides an alternative that the VMM can select, if available. The two
are designed to have very similar APIs.
- Userspace controlled attributes for hardware page
tables (HWPT/iommu_domain). There are currently a few generic attributes
for HWPTs (support dirty tracking, and parent of a nest). This is an
entry point for the userspace iommu driver to control the HW in detail.
- Nested translation support for HWPTs. This is a 2D translation scheme
similar to the CPU where a DMA goes through a first stage to determine
an intermediate address which is then translated trough a second stage
to a physical address.
Like for CPU translation the first stage table would exist in VM
controlled memory and the second stage is in the kernel and matches the
VM's guest to physical map.
As every IOMMU has a unique set of parameter to describe the S1 IO page
table and its associated parameters the userspace IOMMU driver has to
marshal the information into the correct format.
This is 1/3 of the feature, it allows creating the nested translation
and binding it to VFIO devices, however the API to support IOTLB and
ATC invalidation of the stage 1 io page table, and forwarding of IO
faults are still in progress.
The series includes AMD and Intel support for dirty tracking. Intel
support for nested translation.
Along the way are a number of internal items:
- New iommu core items: ops->domain_alloc_user(), ops->set_dirty_tracking,
ops->read_and_clear_dirty(), IOMMU_DOMAIN_NESTED, and iommu_copy_struct_from_user
- UAF fix in iopt_area_split()
- Spelling fixes and some test suite improvement
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Merge tag 'for-linus-iommufd' of git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd
Pull iommufd updates from Jason Gunthorpe:
"This brings three new iommufd capabilities:
- Dirty tracking for DMA.
AMD/ARM/Intel CPUs can now record if a DMA writes to a page in the
IOPTEs within the IO page table. This can be used to generate a
record of what memory is being dirtied by DMA activities during a
VM migration process. A VMM like qemu will combine the IOMMU dirty
bits with the CPU's dirty log to determine what memory to transfer.
VFIO already has a DMA dirty tracking framework that requires PCI
devices to implement tracking HW internally. The iommufd version
provides an alternative that the VMM can select, if available. The
two are designed to have very similar APIs.
- Userspace controlled attributes for hardware page tables
(HWPT/iommu_domain). There are currently a few generic attributes
for HWPTs (support dirty tracking, and parent of a nest). This is
an entry point for the userspace iommu driver to control the HW in
detail.
- Nested translation support for HWPTs. This is a 2D translation
scheme similar to the CPU where a DMA goes through a first stage to
determine an intermediate address which is then translated trough a
second stage to a physical address.
Like for CPU translation the first stage table would exist in VM
controlled memory and the second stage is in the kernel and matches
the VM's guest to physical map.
As every IOMMU has a unique set of parameter to describe the S1 IO
page table and its associated parameters the userspace IOMMU driver
has to marshal the information into the correct format.
This is 1/3 of the feature, it allows creating the nested
translation and binding it to VFIO devices, however the API to
support IOTLB and ATC invalidation of the stage 1 io page table,
and forwarding of IO faults are still in progress.
The series includes AMD and Intel support for dirty tracking. Intel
support for nested translation.
Along the way are a number of internal items:
- New iommu core items: ops->domain_alloc_user(),
ops->set_dirty_tracking, ops->read_and_clear_dirty(),
IOMMU_DOMAIN_NESTED, and iommu_copy_struct_from_user
- UAF fix in iopt_area_split()
- Spelling fixes and some test suite improvement"
* tag 'for-linus-iommufd' of git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd: (52 commits)
iommufd: Organize the mock domain alloc functions closer to Joerg's tree
iommufd/selftest: Fix page-size check in iommufd_test_dirty()
iommufd: Add iopt_area_alloc()
iommufd: Fix missing update of domains_itree after splitting iopt_area
iommu/vt-d: Disallow read-only mappings to nest parent domain
iommu/vt-d: Add nested domain allocation
iommu/vt-d: Set the nested domain to a device
iommu/vt-d: Make domain attach helpers to be extern
iommu/vt-d: Add helper to setup pasid nested translation
iommu/vt-d: Add helper for nested domain allocation
iommu/vt-d: Extend dmar_domain to support nested domain
iommufd: Add data structure for Intel VT-d stage-1 domain allocation
iommu/vt-d: Enhance capability check for nested parent domain allocation
iommufd/selftest: Add coverage for IOMMU_HWPT_ALLOC with nested HWPTs
iommufd/selftest: Add nested domain allocation for mock domain
iommu: Add iommu_copy_struct_from_user helper
iommufd: Add a nested HW pagetable object
iommu: Pass in parent domain with user_data to domain_alloc_user op
iommufd: Share iommufd_hwpt_alloc with IOMMUFD_OBJ_HWPT_NESTED
iommufd: Derive iommufd_hwpt_paging from iommufd_hw_pagetable
...
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# SPDX-License-Identifier: GPL-2.0-only
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# Intel IOMMU support
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config DMAR_TABLE
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bool
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config DMAR_PERF
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bool
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config DMAR_DEBUG
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bool
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config INTEL_IOMMU
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bool "Support for Intel IOMMU using DMA Remapping Devices"
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depends on PCI_MSI && ACPI && X86
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select DMA_OPS
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select IOMMU_API
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select IOMMU_IOVA
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select IOMMUFD_DRIVER if IOMMUFD
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select NEED_DMA_MAP_STATE
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select DMAR_TABLE
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select SWIOTLB
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select PCI_ATS
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select PCI_PRI
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select PCI_PASID
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help
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DMA remapping (DMAR) devices support enables independent address
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translations for Direct Memory Access (DMA) from devices.
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These DMA remapping devices are reported via ACPI tables
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and include PCI device scope covered by these DMA
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remapping devices.
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if INTEL_IOMMU
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config INTEL_IOMMU_DEBUGFS
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bool "Export Intel IOMMU internals in Debugfs"
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depends on IOMMU_DEBUGFS
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select DMAR_PERF
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select DMAR_DEBUG
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help
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!!!WARNING!!!
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DO NOT ENABLE THIS OPTION UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!!!
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Expose Intel IOMMU internals in Debugfs.
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This option is -NOT- intended for production environments, and should
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only be enabled for debugging Intel IOMMU.
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config INTEL_IOMMU_SVM
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bool "Support for Shared Virtual Memory with Intel IOMMU"
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depends on X86_64
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select MMU_NOTIFIER
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select IOMMU_SVA
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help
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Shared Virtual Memory (SVM) provides a facility for devices
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to access DMA resources through process address space by
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means of a Process Address Space ID (PASID).
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config INTEL_IOMMU_DEFAULT_ON
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bool "Enable Intel DMA Remapping Devices by default"
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default y
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help
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Selecting this option will enable a DMAR device at boot time if
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one is found. If this option is not selected, DMAR support can
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be enabled by passing intel_iommu=on to the kernel.
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config INTEL_IOMMU_BROKEN_GFX_WA
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bool "Workaround broken graphics drivers (going away soon)"
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depends on BROKEN && X86
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help
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Current Graphics drivers tend to use physical address
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for DMA and avoid using DMA APIs. Setting this config
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option permits the IOMMU driver to set a unity map for
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all the OS-visible memory. Hence the driver can continue
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to use physical addresses for DMA, at least until this
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option is removed in the 2.6.32 kernel.
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config INTEL_IOMMU_FLOPPY_WA
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def_bool y
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depends on X86
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help
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Floppy disk drivers are known to bypass DMA API calls
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thereby failing to work when IOMMU is enabled. This
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workaround will setup a 1:1 mapping for the first
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16MiB to make floppy (an ISA device) work.
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config INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON
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bool "Enable Intel IOMMU scalable mode by default"
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default y
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help
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Selecting this option will enable by default the scalable mode if
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hardware presents the capability. The scalable mode is defined in
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VT-d 3.0. The scalable mode capability could be checked by reading
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/sys/devices/virtual/iommu/dmar*/intel-iommu/ecap. If this option
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is not selected, scalable mode support could also be enabled by
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passing intel_iommu=sm_on to the kernel. If not sure, please use
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the default value.
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config INTEL_IOMMU_PERF_EVENTS
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def_bool y
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bool "Intel IOMMU performance events"
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depends on INTEL_IOMMU && PERF_EVENTS
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help
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Selecting this option will enable the performance monitoring
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infrastructure in the Intel IOMMU. It collects information about
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key events occurring during operation of the remapping hardware,
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to aid performance tuning and debug. These are available on modern
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processors which support Intel VT-d 4.0 and later.
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endif # INTEL_IOMMU
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