mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-13 14:14:37 +00:00
25d316989e
The clock controller on Meson8/Meson8b/Meson8m2 has three (known) inputs: - "xtal": the main 24MHz crystal - "ddr_pll": some of the audio clocks use the output of the DDR PLL as input - "clk_32k": an optional clock signal which can be connected to GPIOAO_6 (which then has to be switched to the CLK_32K_IN function) Add the inputs to the documentation so we can wire up these inputs in a follow-up patch. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
51 lines
1.7 KiB
Text
51 lines
1.7 KiB
Text
* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
|
|
|
|
The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
|
|
supplies clock to various controllers within the SoC.
|
|
|
|
Required Properties:
|
|
|
|
- compatible: must be one of:
|
|
- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
|
|
- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
|
|
- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
|
|
- #clock-cells: should be 1.
|
|
- #reset-cells: should be 1.
|
|
- clocks: list of clock phandles, one for each entry in clock-names
|
|
- clock-names: should contain the following:
|
|
* "xtal": the 24MHz system oscillator
|
|
* "ddr_pll": the DDR PLL clock
|
|
* "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
|
|
|
|
Parent node should have the following properties :
|
|
- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
|
|
- reg: base address and size of the HHI system control register space.
|
|
|
|
Each clock is assigned an identifier and client nodes can use this identifier
|
|
to specify the clock which they consume. All available clocks are defined as
|
|
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
|
|
used in device tree sources.
|
|
|
|
Similarly a preprocessor macro for each reset line is defined in
|
|
dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
|
|
device tree sources).
|
|
|
|
|
|
Example: Clock controller node:
|
|
|
|
clkc: clock-controller {
|
|
compatible = "amlogic,meson8b-clkc";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
|
|
Example: UART controller node that consumes the clock generated by the clock
|
|
controller:
|
|
|
|
uart_AO: serial@c81004c0 {
|
|
compatible = "amlogic,meson-uart";
|
|
reg = <0xc81004c0 0x14>;
|
|
interrupts = <0 90 1>;
|
|
clocks = <&clkc CLKID_CLK81>;
|
|
};
|