Max Filippov d2e9581f18 xtensa: add missing isync to the cpu_reset TLB code ... commit cd8869f4cb upstream. ITLB entry modifications must be followed by the isync instruction before the new entries are possibly used. cpu_reset lacks one isync between ITLB way 6 initialization and jump to the identity mapping. Add missing isync to xtensa cpu_reset. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2019-08-25 10:50:04 +02:00
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boot	xtensa: xtfpga.dtsi: fix dtc warnings about SPI	2019-05-16 19:42:30 +02:00
configs	xtensa: smp_lx200_defconfig: fix vectors clash	2019-03-13 14:03:12 -07:00
include	xtensa: make sure bFLT stack is 16 byte aligned	2018-11-21 09:24:06 +01:00
kernel	xtensa: add missing isync to the cpu_reset TLB code	2019-08-25 10:50:04 +02:00
lib	xtensa: get rid of zeroing, use RAW_COPY_USER	2017-03-28 18:24:07 -04:00
mm	xtensa: fix high memory/reserved memory collision	2018-02-28 10:19:38 +01:00
oprofile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
platforms	xtensa: ISS: don't allocate memory in platform_setup	2018-09-26 08:38:08 +02:00
variants	xtensa: Added Cadence CSP kernel configuration for Xtensa	2016-09-09 18:39:09 -07:00
Kconfig	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
Kconfig.debug	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
Makefile	xtensa: clean up bootable image build targets	2017-03-01 12:32:50 -08:00