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83e1ada67a
This patch enables presenting Sampled Instruction Address Register (SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended registers for the perf tool. Add these SPR's to sample_reg_mask in the tool side (to use with -I? option). Reviewed-by: Kajol Jain <kjain@linux.ibm.com> Signed-off-by: Athira Jajeev <atrajeev@linux.vnet.ibm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nageswara R Sastry <rnsastry@linux.ibm.com> Cc: linuxppc-dev@lists.ozlabs.org Link: https://lore.kernel.org/r/20211018114948.16830-3-atrajeev@linux.vnet.ibm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
95 lines
2.7 KiB
C
95 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _UAPI_ASM_POWERPC_PERF_REGS_H
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#define _UAPI_ASM_POWERPC_PERF_REGS_H
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enum perf_event_powerpc_regs {
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PERF_REG_POWERPC_R0,
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PERF_REG_POWERPC_R1,
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PERF_REG_POWERPC_R2,
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PERF_REG_POWERPC_R3,
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PERF_REG_POWERPC_R4,
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PERF_REG_POWERPC_R5,
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PERF_REG_POWERPC_R6,
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PERF_REG_POWERPC_R7,
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PERF_REG_POWERPC_R8,
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PERF_REG_POWERPC_R9,
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PERF_REG_POWERPC_R10,
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PERF_REG_POWERPC_R11,
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PERF_REG_POWERPC_R12,
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PERF_REG_POWERPC_R13,
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PERF_REG_POWERPC_R14,
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PERF_REG_POWERPC_R15,
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PERF_REG_POWERPC_R16,
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PERF_REG_POWERPC_R17,
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PERF_REG_POWERPC_R18,
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PERF_REG_POWERPC_R19,
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PERF_REG_POWERPC_R20,
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PERF_REG_POWERPC_R21,
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PERF_REG_POWERPC_R22,
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PERF_REG_POWERPC_R23,
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PERF_REG_POWERPC_R24,
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PERF_REG_POWERPC_R25,
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PERF_REG_POWERPC_R26,
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PERF_REG_POWERPC_R27,
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PERF_REG_POWERPC_R28,
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PERF_REG_POWERPC_R29,
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PERF_REG_POWERPC_R30,
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PERF_REG_POWERPC_R31,
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PERF_REG_POWERPC_NIP,
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PERF_REG_POWERPC_MSR,
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PERF_REG_POWERPC_ORIG_R3,
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PERF_REG_POWERPC_CTR,
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PERF_REG_POWERPC_LINK,
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PERF_REG_POWERPC_XER,
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PERF_REG_POWERPC_CCR,
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PERF_REG_POWERPC_SOFTE,
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PERF_REG_POWERPC_TRAP,
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PERF_REG_POWERPC_DAR,
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PERF_REG_POWERPC_DSISR,
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PERF_REG_POWERPC_SIER,
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PERF_REG_POWERPC_MMCRA,
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/* Extended registers */
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PERF_REG_POWERPC_MMCR0,
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PERF_REG_POWERPC_MMCR1,
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PERF_REG_POWERPC_MMCR2,
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PERF_REG_POWERPC_MMCR3,
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PERF_REG_POWERPC_SIER2,
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PERF_REG_POWERPC_SIER3,
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PERF_REG_POWERPC_PMC1,
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PERF_REG_POWERPC_PMC2,
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PERF_REG_POWERPC_PMC3,
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PERF_REG_POWERPC_PMC4,
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PERF_REG_POWERPC_PMC5,
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PERF_REG_POWERPC_PMC6,
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PERF_REG_POWERPC_SDAR,
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PERF_REG_POWERPC_SIAR,
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/* Max mask value for interrupt regs w/o extended regs */
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PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
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/* Max mask value for interrupt regs including extended regs */
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PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_SIAR + 1,
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};
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#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
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/*
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* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300
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* includes 11 SPRS from MMCR0 to SIAR excluding the
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* unsupported SPRS MMCR3, SIER2 and SIER3.
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*/
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#define PERF_REG_PMU_MASK_300 \
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((1ULL << PERF_REG_POWERPC_MMCR0) | (1ULL << PERF_REG_POWERPC_MMCR1) | \
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(1ULL << PERF_REG_POWERPC_MMCR2) | (1ULL << PERF_REG_POWERPC_PMC1) | \
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(1ULL << PERF_REG_POWERPC_PMC2) | (1ULL << PERF_REG_POWERPC_PMC3) | \
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(1ULL << PERF_REG_POWERPC_PMC4) | (1ULL << PERF_REG_POWERPC_PMC5) | \
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(1ULL << PERF_REG_POWERPC_PMC6) | (1ULL << PERF_REG_POWERPC_SDAR) | \
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(1ULL << PERF_REG_POWERPC_SIAR))
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/*
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* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31
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* includes 14 SPRs from MMCR0 to SIAR.
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*/
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#define PERF_REG_PMU_MASK_31 \
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(PERF_REG_PMU_MASK_300 | (1ULL << PERF_REG_POWERPC_MMCR3) | \
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(1ULL << PERF_REG_POWERPC_SIER2) | (1ULL << PERF_REG_POWERPC_SIER3))
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#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
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