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4525412a50
Dealing with HW related matters in tmc_read_prepare/unprepare becomes convoluted when many cases need to be handled distinctively. As such moving processing related to HW setup to individual driver files and keep the core driver generic. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
264 lines
6.5 KiB
C
264 lines
6.5 KiB
C
/*
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* Copyright(C) 2016 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/coresight.h>
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#include "coresight-priv.h"
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#include "coresight-tmc.h"
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void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
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{
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/* Zero out the memory to help with debug */
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memset(drvdata->buf, 0, drvdata->size);
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CS_UNLOCK(drvdata->base);
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/* Wait for TMCSReady bit to be set */
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tmc_wait_for_tmcready(drvdata);
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writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
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writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
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TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
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TMC_FFCR_TRIGON_TRIGIN,
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drvdata->base + TMC_FFCR);
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writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
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tmc_enable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
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{
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enum tmc_mem_intf_width memwidth;
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u8 memwords;
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char *bufp;
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u32 read_data;
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int i;
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memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10);
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if (memwidth == TMC_MEM_INTF_WIDTH_32BITS)
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memwords = 1;
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else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS)
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memwords = 2;
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else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS)
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memwords = 4;
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else
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memwords = 8;
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bufp = drvdata->buf;
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while (1) {
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for (i = 0; i < memwords; i++) {
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read_data = readl_relaxed(drvdata->base + TMC_RRD);
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if (read_data == 0xFFFFFFFF)
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return;
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memcpy(bufp, &read_data, 4);
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bufp += 4;
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}
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}
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}
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static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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tmc_flush_and_stop(drvdata);
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tmc_etb_dump_hw(drvdata);
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tmc_disable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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/* Wait for TMCSReady bit to be set */
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tmc_wait_for_tmcready(drvdata);
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writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
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writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
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drvdata->base + TMC_FFCR);
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writel_relaxed(0x0, drvdata->base + TMC_BUFWM);
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tmc_enable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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tmc_flush_and_stop(drvdata);
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tmc_disable_hw(drvdata);
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CS_LOCK(drvdata->base);
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}
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static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode)
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{
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unsigned long flags;
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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spin_lock_irqsave(&drvdata->spinlock, flags);
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if (drvdata->reading) {
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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return -EBUSY;
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}
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tmc_etb_enable_hw(drvdata);
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drvdata->enable = true;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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dev_info(drvdata->dev, "TMC-ETB/ETF enabled\n");
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return 0;
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}
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static void tmc_disable_etf_sink(struct coresight_device *csdev)
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{
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unsigned long flags;
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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spin_lock_irqsave(&drvdata->spinlock, flags);
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if (drvdata->reading) {
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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return;
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}
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tmc_etb_disable_hw(drvdata);
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drvdata->enable = false;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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dev_info(drvdata->dev, "TMC-ETB/ETF disabled\n");
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}
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static int tmc_enable_etf_link(struct coresight_device *csdev,
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int inport, int outport)
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{
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unsigned long flags;
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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spin_lock_irqsave(&drvdata->spinlock, flags);
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if (drvdata->reading) {
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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return -EBUSY;
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}
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tmc_etf_enable_hw(drvdata);
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drvdata->enable = true;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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dev_info(drvdata->dev, "TMC-ETF enabled\n");
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return 0;
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}
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static void tmc_disable_etf_link(struct coresight_device *csdev,
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int inport, int outport)
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{
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unsigned long flags;
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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spin_lock_irqsave(&drvdata->spinlock, flags);
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if (drvdata->reading) {
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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return;
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}
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tmc_etf_disable_hw(drvdata);
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drvdata->enable = false;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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dev_info(drvdata->dev, "TMC disabled\n");
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}
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static const struct coresight_ops_sink tmc_etf_sink_ops = {
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.enable = tmc_enable_etf_sink,
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.disable = tmc_disable_etf_sink,
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};
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static const struct coresight_ops_link tmc_etf_link_ops = {
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.enable = tmc_enable_etf_link,
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.disable = tmc_disable_etf_link,
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};
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const struct coresight_ops tmc_etb_cs_ops = {
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.sink_ops = &tmc_etf_sink_ops,
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};
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const struct coresight_ops tmc_etf_cs_ops = {
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.sink_ops = &tmc_etf_sink_ops,
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.link_ops = &tmc_etf_link_ops,
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};
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int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
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{
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enum tmc_mode mode;
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int ret = 0;
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unsigned long flags;
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/* config types are set a boot time and never change */
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if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB &&
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drvdata->config_type != TMC_CONFIG_TYPE_ETF))
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return -EINVAL;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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/* There is no point in reading a TMC in HW FIFO mode */
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mode = readl_relaxed(drvdata->base + TMC_MODE);
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if (mode != TMC_MODE_CIRCULAR_BUFFER) {
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ret = -EINVAL;
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goto out;
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}
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/* Disable the TMC if need be */
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if (drvdata->enable)
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tmc_etb_disable_hw(drvdata);
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drvdata->reading = true;
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out:
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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return ret;
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}
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int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata)
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{
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enum tmc_mode mode;
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unsigned long flags;
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/* config types are set a boot time and never change */
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if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB &&
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drvdata->config_type != TMC_CONFIG_TYPE_ETF))
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return -EINVAL;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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/* There is no point in reading a TMC in HW FIFO mode */
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mode = readl_relaxed(drvdata->base + TMC_MODE);
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if (mode != TMC_MODE_CIRCULAR_BUFFER) {
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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return -EINVAL;
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}
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/* Re-enable the TMC if need be */
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if (drvdata->enable)
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tmc_etb_enable_hw(drvdata);
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drvdata->reading = false;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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return 0;
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}
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