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bb6ae9e653
Various pixel formats and plane scaling impose additional constraints
on the cdclk frequency. Provide a new plane->min_cdclk() hook that
will be used to compute the minimum acceptable cdclk frequency for
each plane.
Annoyingly on some platforms the numer of active planes affects
this calculation so we must also toss in more planes into the
state when the number of active planes changes.
The sequence of state computation must also be changed:
1. check_plane() (updates plane's visibility etc.)
2. figure out if more planes now require update min_cdclk
computaion
3. calculate the new min cdclk for each plane in the state
4. if the minimum of any plane now exceeds the current
logical cdclk we recompute the cdclk
4. during cdclk computation take the planes' min_cdclk into
accoutn
5. follow the normal cdclk programming to change the
cdclk frequency. This may now require a modeset (except
on bxt/glk in some cases), which either succeeds or
fails depending on whether userspace has given
us permission to perform a modeset or not.
v2: Fix plane id check in intel_crtc_add_planes_to_state()
Only print the debug message when cdclk needs bumping
Use dev_priv->cdclk... as the old state explicitly
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015193035.25982-5-ville.syrjala@linux.intel.com
59 lines
1.9 KiB
C
59 lines
1.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_SPRITE_H__
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#define __INTEL_SPRITE_H__
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#include <linux/types.h>
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#include "intel_display.h"
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struct drm_device;
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struct drm_display_mode;
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struct drm_file;
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struct drm_i915_private;
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struct intel_crtc_state;
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struct intel_plane_state;
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int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
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int usecs);
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struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
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enum pipe pipe, int plane);
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int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
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void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
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int intel_plane_check_stride(const struct intel_plane_state *plane_state);
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int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
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int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
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struct intel_plane *
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skl_universal_plane_create(struct drm_i915_private *dev_priv,
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enum pipe pipe, enum plane_id plane_id);
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static inline bool icl_is_nv12_y_plane(enum plane_id id)
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{
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/* Don't need to do a gen check, these planes are only available on gen11 */
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if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
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return true;
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return false;
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}
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static inline u8 icl_hdr_plane_mask(void)
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{
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return BIT(PLANE_PRIMARY) |
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BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
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}
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bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
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int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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#endif /* __INTEL_SPRITE_H__ */
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