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![Maxim Kochetkov](/assets/img/avatar_default.png)
Depending on hardware implementaion of DWC I2S controller may support TDM mode if enabled in SoC at design time. Unfortunately there is no way to detect TDM capability for DWC by reading registers. Anyway, if such capability enabled, TDM mode can be enabled and configured by dai-tdm-slot-* DT options. Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru> Link: https://lore.kernel.org/r/20230622200031.120168-1-fido_max@inbox.ru Signed-off-by: Mark Brown <broonie@kernel.org>
266 lines
6.8 KiB
C
266 lines
6.8 KiB
C
/*
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* ALSA SoC Synopsys PIO PCM for I2S driver
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*
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* sound/soc/dwc/designware_pcm.c
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*
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* Copyright (C) 2016 Synopsys
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* Jose Abreu <joabreu@synopsys.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/rcupdate.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include "local.h"
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#define BUFFER_BYTES_MAX (3 * 2 * 8 * PERIOD_BYTES_MIN)
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#define PERIOD_BYTES_MIN 4096
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#define PERIODS_MIN 2
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#define dw_pcm_tx_fn(sample_bits) \
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static unsigned int dw_pcm_tx_##sample_bits(struct dw_i2s_dev *dev, \
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struct snd_pcm_runtime *runtime, unsigned int tx_ptr, \
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bool *period_elapsed) \
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{ \
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const u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
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unsigned int period_pos = tx_ptr % runtime->period_size; \
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int i; \
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\
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for (i = 0; i < dev->fifo_th; i++) { \
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iowrite32(p[tx_ptr][0], dev->i2s_base + dev->l_reg); \
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iowrite32(p[tx_ptr][1], dev->i2s_base + dev->r_reg); \
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period_pos++; \
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if (++tx_ptr >= runtime->buffer_size) \
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tx_ptr = 0; \
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} \
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*period_elapsed = period_pos >= runtime->period_size; \
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return tx_ptr; \
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}
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#define dw_pcm_rx_fn(sample_bits) \
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static unsigned int dw_pcm_rx_##sample_bits(struct dw_i2s_dev *dev, \
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struct snd_pcm_runtime *runtime, unsigned int rx_ptr, \
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bool *period_elapsed) \
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{ \
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u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
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unsigned int period_pos = rx_ptr % runtime->period_size; \
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int i; \
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\
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for (i = 0; i < dev->fifo_th; i++) { \
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p[rx_ptr][0] = ioread32(dev->i2s_base + dev->l_reg); \
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p[rx_ptr][1] = ioread32(dev->i2s_base + dev->r_reg); \
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period_pos++; \
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if (++rx_ptr >= runtime->buffer_size) \
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rx_ptr = 0; \
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} \
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*period_elapsed = period_pos >= runtime->period_size; \
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return rx_ptr; \
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}
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dw_pcm_tx_fn(16);
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dw_pcm_tx_fn(32);
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dw_pcm_rx_fn(16);
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dw_pcm_rx_fn(32);
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#undef dw_pcm_tx_fn
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#undef dw_pcm_rx_fn
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static const struct snd_pcm_hardware dw_pcm_hardware = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_BLOCK_TRANSFER,
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.rates = SNDRV_PCM_RATE_32000 |
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SNDRV_PCM_RATE_44100 |
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SNDRV_PCM_RATE_48000,
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.rate_min = 32000,
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.rate_max = 48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 2,
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.channels_max = 2,
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.buffer_bytes_max = BUFFER_BYTES_MAX,
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.period_bytes_min = PERIOD_BYTES_MIN,
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.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
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.periods_min = PERIODS_MIN,
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.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
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.fifo_size = 16,
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};
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static void dw_pcm_transfer(struct dw_i2s_dev *dev, bool push)
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{
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struct snd_pcm_substream *substream;
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bool active, period_elapsed;
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rcu_read_lock();
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if (push)
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substream = rcu_dereference(dev->tx_substream);
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else
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substream = rcu_dereference(dev->rx_substream);
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active = substream && snd_pcm_running(substream);
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if (active) {
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unsigned int ptr;
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unsigned int new_ptr;
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if (push) {
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ptr = READ_ONCE(dev->tx_ptr);
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new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
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&period_elapsed);
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cmpxchg(&dev->tx_ptr, ptr, new_ptr);
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} else {
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ptr = READ_ONCE(dev->rx_ptr);
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new_ptr = dev->rx_fn(dev, substream->runtime, ptr,
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&period_elapsed);
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cmpxchg(&dev->rx_ptr, ptr, new_ptr);
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}
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if (period_elapsed)
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snd_pcm_period_elapsed(substream);
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}
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rcu_read_unlock();
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}
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void dw_pcm_push_tx(struct dw_i2s_dev *dev)
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{
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dw_pcm_transfer(dev, true);
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}
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void dw_pcm_pop_rx(struct dw_i2s_dev *dev)
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{
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dw_pcm_transfer(dev, false);
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}
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static int dw_pcm_open(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
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snd_soc_set_runtime_hwparams(substream, &dw_pcm_hardware);
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snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
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runtime->private_data = dev;
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return 0;
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}
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static int dw_pcm_close(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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synchronize_rcu();
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return 0;
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}
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static int dw_pcm_hw_params(struct snd_soc_component *component,
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struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hw_params)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct dw_i2s_dev *dev = runtime->private_data;
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switch (params_channels(hw_params)) {
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case 2:
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break;
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default:
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dev_err(dev->dev, "invalid channels number\n");
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return -EINVAL;
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}
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switch (params_format(hw_params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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dev->tx_fn = dw_pcm_tx_16;
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dev->rx_fn = dw_pcm_rx_16;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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case SNDRV_PCM_FORMAT_S32_LE:
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dev->tx_fn = dw_pcm_tx_32;
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dev->rx_fn = dw_pcm_rx_32;
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break;
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default:
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dev_err(dev->dev, "invalid format\n");
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return -EINVAL;
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}
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return 0;
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}
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static int dw_pcm_trigger(struct snd_soc_component *component,
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struct snd_pcm_substream *substream, int cmd)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct dw_i2s_dev *dev = runtime->private_data;
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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WRITE_ONCE(dev->tx_ptr, 0);
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rcu_assign_pointer(dev->tx_substream, substream);
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} else {
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WRITE_ONCE(dev->rx_ptr, 0);
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rcu_assign_pointer(dev->rx_substream, substream);
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}
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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rcu_assign_pointer(dev->tx_substream, NULL);
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else
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rcu_assign_pointer(dev->rx_substream, NULL);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static snd_pcm_uframes_t dw_pcm_pointer(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct dw_i2s_dev *dev = runtime->private_data;
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snd_pcm_uframes_t pos;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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pos = READ_ONCE(dev->tx_ptr);
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else
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pos = READ_ONCE(dev->rx_ptr);
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return pos < runtime->buffer_size ? pos : 0;
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}
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static int dw_pcm_new(struct snd_soc_component *component,
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struct snd_soc_pcm_runtime *rtd)
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{
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size_t size = dw_pcm_hardware.buffer_bytes_max;
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snd_pcm_set_managed_buffer_all(rtd->pcm,
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SNDRV_DMA_TYPE_CONTINUOUS,
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NULL, size, size);
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return 0;
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}
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static const struct snd_soc_component_driver dw_pcm_component = {
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.open = dw_pcm_open,
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.close = dw_pcm_close,
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.hw_params = dw_pcm_hw_params,
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.trigger = dw_pcm_trigger,
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.pointer = dw_pcm_pointer,
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.pcm_construct = dw_pcm_new,
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};
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int dw_pcm_register(struct platform_device *pdev)
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{
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return devm_snd_soc_register_component(&pdev->dev, &dw_pcm_component,
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NULL, 0);
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}
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