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![George G. Davis](/assets/img/avatar_default.png)
Commit 1c9d3df5e8
added function prototype
__flush_dcache_page() in include/asm-arm/cacheflush.h. So we can remove
the prototype for same in arch/arm/mm/fault-armv.c since it is now
redundant to have it there.
Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
217 lines
5.2 KiB
C
217 lines
5.2 KiB
C
/*
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* linux/arch/arm/mm/fault-armv.c
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*
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* Copyright (C) 1995 Linus Torvalds
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* Modifications for ARM processor (c) 1995-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/bitops.h>
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/pagemap.h>
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#include <asm/cacheflush.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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static unsigned long shared_pte_mask = L_PTE_CACHEABLE;
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/*
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* We take the easy way out of this problem - we make the
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* PTE uncacheable. However, we leave the write buffer on.
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*
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* Note that the pte lock held when calling update_mmu_cache must also
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* guard the pte (somewhere else in the same mm) that we modify here.
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* Therefore those configurations which might call adjust_pte (those
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* without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
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*/
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static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
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{
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pgd_t *pgd;
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pmd_t *pmd;
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pte_t *pte, entry;
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int ret = 0;
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pgd = pgd_offset(vma->vm_mm, address);
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if (pgd_none(*pgd))
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goto no_pgd;
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if (pgd_bad(*pgd))
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goto bad_pgd;
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pmd = pmd_offset(pgd, address);
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if (pmd_none(*pmd))
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goto no_pmd;
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if (pmd_bad(*pmd))
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goto bad_pmd;
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pte = pte_offset_map(pmd, address);
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entry = *pte;
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/*
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* If this page isn't present, or is already setup to
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* fault (ie, is old), we can safely ignore any issues.
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*/
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if (pte_present(entry) && pte_val(entry) & shared_pte_mask) {
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flush_cache_page(vma, address, pte_pfn(entry));
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pte_val(entry) &= ~shared_pte_mask;
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set_pte_at(vma->vm_mm, address, pte, entry);
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flush_tlb_page(vma, address);
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ret = 1;
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}
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pte_unmap(pte);
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return ret;
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bad_pgd:
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pgd_ERROR(*pgd);
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pgd_clear(pgd);
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no_pgd:
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return 0;
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bad_pmd:
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pmd_ERROR(*pmd);
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pmd_clear(pmd);
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no_pmd:
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return 0;
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}
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static void
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make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
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{
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struct mm_struct *mm = vma->vm_mm;
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struct vm_area_struct *mpnt;
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struct prio_tree_iter iter;
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unsigned long offset;
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pgoff_t pgoff;
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int aliases = 0;
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pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
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/*
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* If we have any shared mappings that are in the same mm
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* space, then we need to handle them specially to maintain
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* cache coherency.
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*/
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flush_dcache_mmap_lock(mapping);
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vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
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/*
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* If this VMA is not in our MM, we can ignore it.
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* Note that we intentionally mask out the VMA
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* that we are fixing up.
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*/
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if (mpnt->vm_mm != mm || mpnt == vma)
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continue;
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if (!(mpnt->vm_flags & VM_MAYSHARE))
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continue;
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offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
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aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
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}
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flush_dcache_mmap_unlock(mapping);
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if (aliases)
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adjust_pte(vma, addr);
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else
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flush_cache_page(vma, addr, pfn);
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}
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/*
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* Take care of architecture specific things when placing a new PTE into
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* a page table, or changing an existing PTE. Basically, there are two
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* things that we need to take care of:
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*
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* 1. If PG_dcache_dirty is set for the page, we need to ensure
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* that any cache entries for the kernels virtual memory
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* range are written back to the page.
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* 2. If we have multiple shared mappings of the same space in
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* an object, we need to deal with the cache aliasing issues.
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*
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* Note that the pte lock will be held.
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*/
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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{
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unsigned long pfn = pte_pfn(pte);
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struct address_space *mapping;
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struct page *page;
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if (!pfn_valid(pfn))
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return;
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page = pfn_to_page(pfn);
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mapping = page_mapping(page);
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if (mapping) {
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int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
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if (dirty)
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__flush_dcache_page(mapping, page);
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if (cache_is_vivt())
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make_coherent(mapping, vma, addr, pfn);
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}
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}
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/*
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* Check whether the write buffer has physical address aliasing
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* issues. If it has, we need to avoid them for the case where
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* we have several shared mappings of the same object in user
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* space.
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*/
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static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
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{
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register unsigned long zero = 0, one = 1, val;
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local_irq_disable();
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mb();
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*p1 = one;
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mb();
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*p2 = zero;
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mb();
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val = *p1;
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mb();
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local_irq_enable();
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return val != zero;
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}
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void __init check_writebuffer_bugs(void)
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{
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struct page *page;
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const char *reason;
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unsigned long v = 1;
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printk(KERN_INFO "CPU: Testing write buffer coherency: ");
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page = alloc_page(GFP_KERNEL);
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if (page) {
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unsigned long *p1, *p2;
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pgprot_t prot = __pgprot(L_PTE_PRESENT|L_PTE_YOUNG|
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L_PTE_DIRTY|L_PTE_WRITE|
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L_PTE_BUFFERABLE);
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p1 = vmap(&page, 1, VM_IOREMAP, prot);
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p2 = vmap(&page, 1, VM_IOREMAP, prot);
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if (p1 && p2) {
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v = check_writebuffer(p1, p2);
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reason = "enabling work-around";
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} else {
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reason = "unable to map memory\n";
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}
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vunmap(p1);
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vunmap(p2);
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put_page(page);
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} else {
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reason = "unable to grab page\n";
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}
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if (v) {
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printk("failed, %s\n", reason);
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shared_pte_mask |= L_PTE_BUFFERABLE;
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} else {
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printk("ok\n");
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}
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}
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