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751ba79cc5
This patch uses the vpermxor instruction to optimise the raid6 Q syndrome. This instruction was made available with POWER8, ISA version 2.07. It allows for both vperm and vxor instructions to be done in a single instruction. This has been tested for correctness on a ppc64le vm with a basic RAID6 setup containing 5 drives. The performance benchmarks are from the raid6test in the /lib/raid6/test directory. These results are from an IBM Firestone machine with ppc64le architecture. The benchmark results show a 35% speed increase over the best existing algorithm for powerpc (altivec). The raid6test has also been run on a big-endian ppc64 vm to ensure it also works for big-endian architectures. Performance benchmarks: raid6: altivecx4 gen() 18773 MB/s raid6: altivecx8 gen() 19438 MB/s raid6: vpermxor4 gen() 25112 MB/s raid6: vpermxor8 gen() 26279 MB/s Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by: Daniel Axtens <dja@axtens.net> [mpe: Add VPERMXOR macro so we can build with old binutils] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
105 lines
2.7 KiB
Ucode
105 lines
2.7 KiB
Ucode
/*
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* Copyright 2017, Matt Brown, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* vpermxor$#.c
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*
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* Based on H. Peter Anvin's paper - The mathematics of RAID-6
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*
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* $#-way unrolled portable integer math RAID-6 instruction set
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* This file is postprocessed using unroll.awk
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*
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* vpermxor$#.c makes use of the vpermxor instruction to optimise the RAID6 Q
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* syndrome calculations.
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* This can be run on systems which have both Altivec and vpermxor instruction.
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*
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* This instruction was introduced in POWER8 - ISA v2.07.
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*/
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#include <linux/raid/pq.h>
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#ifdef CONFIG_ALTIVEC
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#include <altivec.h>
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#ifdef __KERNEL__
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#include <asm/cputable.h>
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#include <asm/ppc-opcode.h>
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#include <asm/switch_to.h>
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#endif
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typedef vector unsigned char unative_t;
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#define NSIZE sizeof(unative_t)
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static const vector unsigned char gf_low = {0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14,
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0x12, 0x10, 0x0e, 0x0c, 0x0a, 0x08,
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0x06, 0x04, 0x02,0x00};
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static const vector unsigned char gf_high = {0xfd, 0xdd, 0xbd, 0x9d, 0x7d, 0x5d,
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0x3d, 0x1d, 0xe0, 0xc0, 0xa0, 0x80,
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0x60, 0x40, 0x20, 0x00};
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static void noinline raid6_vpermxor$#_gen_syndrome_real(int disks, size_t bytes,
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void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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unative_t wp$$, wq$$, wd$$;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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for (d = 0; d < bytes; d += NSIZE*$#) {
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wp$$ = wq$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
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for (z = z0-1; z>=0; z--) {
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wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE];
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/* P syndrome */
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wp$$ = vec_xor(wp$$, wd$$);
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/* Q syndrome */
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asm(VPERMXOR(%0,%1,%2,%3):"=v"(wq$$):"v"(gf_high), "v"(gf_low), "v"(wq$$));
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wq$$ = vec_xor(wq$$, wd$$);
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}
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*(unative_t *)&p[d+NSIZE*$$] = wp$$;
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*(unative_t *)&q[d+NSIZE*$$] = wq$$;
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}
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}
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static void raid6_vpermxor$#_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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preempt_disable();
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enable_kernel_altivec();
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raid6_vpermxor$#_gen_syndrome_real(disks, bytes, ptrs);
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disable_kernel_altivec();
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preempt_enable();
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}
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int raid6_have_altivec_vpermxor(void);
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#if $# == 1
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int raid6_have_altivec_vpermxor(void)
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{
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/* Check if arch has both altivec and the vpermxor instructions */
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# ifdef __KERNEL__
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return (cpu_has_feature(CPU_FTR_ALTIVEC_COMP) &&
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cpu_has_feature(CPU_FTR_ARCH_207S));
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# else
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return 1;
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#endif
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}
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#endif
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const struct raid6_calls raid6_vpermxor$# = {
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raid6_vpermxor$#_gen_syndrome,
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NULL,
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raid6_have_altivec_vpermxor,
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"vpermxor$#",
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0
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};
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#endif
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