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a43d8c101e
Remove the depencency on the IOMMU IDR register, as it may not be accessible depending on the security configuraton. This involves moving the NCB field of IDR into the platform data. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef MSM_IOMMU_H
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#define MSM_IOMMU_H
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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/* Sharability attributes of MSM IOMMU mappings */
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#define MSM_IOMMU_ATTR_NON_SH 0x0
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#define MSM_IOMMU_ATTR_SH 0x4
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/* Cacheability attributes of MSM IOMMU mappings */
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#define MSM_IOMMU_ATTR_NONCACHED 0x0
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#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
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#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
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#define MSM_IOMMU_ATTR_CACHED_WT 0x3
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/* Mask for the cache policy attribute */
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#define MSM_IOMMU_CP_MASK 0x03
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/* Maximum number of Machine IDs that we are allowing to be mapped to the same
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* context bank. The number of MIDs mapped to the same CB does not affect
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* performance, but there is a practical limit on how many distinct MIDs may
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* be present. These mappings are typically determined at design time and are
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* not expected to change at run time.
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*/
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#define MAX_NUM_MIDS 32
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/**
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* struct msm_iommu_dev - a single IOMMU hardware instance
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* name Human-readable name given to this IOMMU HW instance
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* ncb Number of context banks present on this IOMMU HW instance
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*/
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struct msm_iommu_dev {
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const char *name;
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int ncb;
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};
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/**
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* struct msm_iommu_ctx_dev - an IOMMU context bank instance
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* name Human-readable name given to this context bank
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* num Index of this context bank within the hardware
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* mids List of Machine IDs that are to be mapped into this context
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* bank, terminated by -1. The MID is a set of signals on the
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* AXI bus that identifies the function associated with a specific
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* memory request. (See ARM spec).
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*/
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struct msm_iommu_ctx_dev {
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const char *name;
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int num;
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int mids[MAX_NUM_MIDS];
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};
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/**
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* struct msm_iommu_drvdata - A single IOMMU hardware instance
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* @base: IOMMU config port base address (VA)
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* @ncb The number of contexts on this IOMMU
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* @irq: Interrupt number
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* @clk: The bus clock for this IOMMU hardware instance
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* @pclk: The clock for the IOMMU bus interconnect
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*
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* A msm_iommu_drvdata holds the global driver data about a single piece
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* of an IOMMU hardware instance.
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*/
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struct msm_iommu_drvdata {
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void __iomem *base;
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int irq;
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int ncb;
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struct clk *clk;
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struct clk *pclk;
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};
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/**
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* struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
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* @num: Hardware context number of this context
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* @pdev: Platform device associated wit this HW instance
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* @attached_elm: List element for domains to track which devices are
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* attached to them
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*
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* A msm_iommu_ctx_drvdata holds the driver data for a single context bank
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* within each IOMMU hardware instance
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*/
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struct msm_iommu_ctx_drvdata {
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int num;
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struct platform_device *pdev;
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struct list_head attached_elm;
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};
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/*
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* Look up an IOMMU context device by its context name. NULL if none found.
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* Useful for testing and drivers that do not yet fully have IOMMU stuff in
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* their platform devices.
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*/
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struct device *msm_iommu_get_ctx(const char *ctx_name);
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/*
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* Interrupt handler for the IOMMU context fault interrupt. Hooking the
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* interrupt is not supported in the API yet, but this will print an error
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* message and dump useful IOMMU registers.
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*/
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irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
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#endif
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