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![Thomas Gleixner](/assets/img/avatar_default.png)
Use irq_set_chip_and_handler() instead. Converted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
172 lines
4.2 KiB
C
172 lines
4.2 KiB
C
/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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static unsigned int int_enable;
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static unsigned int wake_enable;
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static struct sirc_regs_t sirc_regs = {
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.int_enable = SPSS_SIRC_INT_ENABLE,
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.int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR,
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.int_enable_set = SPSS_SIRC_INT_ENABLE_SET,
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.int_type = SPSS_SIRC_INT_TYPE,
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.int_polarity = SPSS_SIRC_INT_POLARITY,
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.int_clear = SPSS_SIRC_INT_CLEAR,
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};
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static struct sirc_cascade_regs sirc_reg_table[] = {
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{
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.int_status = SPSS_SIRC_IRQ_STATUS,
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.cascade_irq = INT_SIRC_0,
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}
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};
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/* Mask off the given interrupt. Keep the int_enable mask in sync with
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the enable reg, so it can be restored after power collapse. */
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static void sirc_irq_mask(struct irq_data *d)
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{
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unsigned int mask;
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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writel(mask, sirc_regs.int_enable_clear);
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int_enable &= ~mask;
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return;
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}
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/* Unmask the given interrupt. Keep the int_enable mask in sync with
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the enable reg, so it can be restored after power collapse. */
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static void sirc_irq_unmask(struct irq_data *d)
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{
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unsigned int mask;
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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writel(mask, sirc_regs.int_enable_set);
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int_enable |= mask;
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return;
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}
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static void sirc_irq_ack(struct irq_data *d)
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{
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unsigned int mask;
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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writel(mask, sirc_regs.int_clear);
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return;
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}
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static int sirc_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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unsigned int mask;
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/* Used to set the interrupt enable mask during power collapse. */
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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if (on)
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wake_enable |= mask;
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else
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wake_enable &= ~mask;
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return 0;
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}
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static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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unsigned int mask;
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unsigned int val;
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mask = 1 << (d->irq - FIRST_SIRC_IRQ);
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val = readl(sirc_regs.int_polarity);
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if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
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val |= mask;
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else
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val &= ~mask;
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writel(val, sirc_regs.int_polarity);
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val = readl(sirc_regs.int_type);
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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val |= mask;
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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} else {
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val &= ~mask;
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__irq_set_handler_locked(d->irq, handle_level_irq);
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}
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writel(val, sirc_regs.int_type);
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return 0;
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}
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/* Finds the pending interrupt on the passed cascade irq and redrives it */
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static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int reg = 0;
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unsigned int sirq;
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unsigned int status;
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while ((reg < ARRAY_SIZE(sirc_reg_table)) &&
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(sirc_reg_table[reg].cascade_irq != irq))
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reg++;
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status = readl(sirc_reg_table[reg].int_status);
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status &= SIRC_MASK;
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if (status == 0)
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return;
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for (sirq = 0;
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(sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0);
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sirq++)
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;
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generic_handle_irq(sirq+FIRST_SIRC_IRQ);
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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}
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static struct irq_chip sirc_irq_chip = {
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.name = "sirc",
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.irq_ack = sirc_irq_ack,
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.irq_mask = sirc_irq_mask,
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.irq_unmask = sirc_irq_unmask,
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.irq_set_wake = sirc_irq_set_wake,
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.irq_set_type = sirc_irq_set_type,
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};
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void __init msm_init_sirc(void)
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{
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int i;
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int_enable = 0;
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wake_enable = 0;
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for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
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irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
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irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
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sirc_irq_handler);
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irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
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}
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return;
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}
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