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![Marc Zyngier](/assets/img/avatar_default.png)
sched_clock() is yet another blocker on the road to the single image. This patch implements an idea by Russell King: http://www.spinics.net/lists/linux-omap/msg49561.html Instead of asking the platform to implement both sched_clock() itself and the rollover callback, simply register a read() function, and let the ARM code care about sched_clock() itself, the conversion to ns and the rollover. sched_clock() uses this read() function as an indirection to the platform code. If the platform doesn't provide a read(), the code falls back to the jiffy counter (just like the default sched_clock). This allow some simplifications and possibly some footprint gain when multiple platforms are compiled in. Among the drawbacks, the removal of the *_fixed_sched_clock optimization which could negatively impact some platforms (sa1100, tegra, versatile and omap). Tested on 11MPCore, OMAP4 and Tegra. Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Eric Miao <eric.y.miao@gmail.com> Cc: Colin Cross <ccross@android.com> Cc: Erik Gilling <konkers@android.com> Cc: Olof Johansson <olof@lixom.net> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Alessandro Rubini <rubini@unipv.it> Cc: STEricsson <STEricsson_nomadik_linux@list.st.com> Cc: Lennert Buytenhek <kernel@wantstofly.org> Cc: Ben Dooks <ben-linux@fluff.org> Tested-by: Jamie Iles <jamie@jamieiles.com> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Krzysztof Halasa <khc@pm.waw.pl> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
229 lines
5.2 KiB
C
229 lines
5.2 KiB
C
/*
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* arch/arm/plat-orion/time.c
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*
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* Marvell Orion SoC timer handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Timer 0 is used as free-running clocksource, while timer 1 is
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* used as clock_event_device.
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*/
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#include <linux/kernel.h>
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#include <linux/timer.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/sched_clock.h>
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/*
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* MBus bridge block registers.
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*/
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#define BRIDGE_CAUSE_OFF 0x0110
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#define BRIDGE_MASK_OFF 0x0114
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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/*
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* Timer block registers.
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*/
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#define TIMER_CTRL_OFF 0x0000
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#define TIMER0_EN 0x0001
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#define TIMER0_RELOAD_EN 0x0002
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#define TIMER1_EN 0x0004
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#define TIMER1_RELOAD_EN 0x0008
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#define TIMER0_RELOAD_OFF 0x0010
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#define TIMER0_VAL_OFF 0x0014
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#define TIMER1_RELOAD_OFF 0x0018
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#define TIMER1_VAL_OFF 0x001c
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/*
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* SoC-specific data.
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*/
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static void __iomem *bridge_base;
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static u32 bridge_timer1_clr_mask;
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static void __iomem *timer_base;
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/*
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* Number of timer ticks per jiffy.
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*/
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static u32 ticks_per_jiffy;
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/*
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* Orion's sched_clock implementation. It has a resolution of
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* at least 7.5ns (133MHz TCLK).
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*/
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static u32 notrace orion_read_sched_clock(void)
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{
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return ~readl(timer_base + TIMER0_VAL_OFF);
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}
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/*
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* Clockevent handling.
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*/
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static int
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orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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unsigned long flags;
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u32 u;
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if (delta == 0)
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return -ETIME;
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local_irq_save(flags);
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/*
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* Clear and enable clockevent timer interrupt.
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*/
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writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
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u = readl(bridge_base + BRIDGE_MASK_OFF);
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u |= BRIDGE_INT_TIMER1;
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writel(u, bridge_base + BRIDGE_MASK_OFF);
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/*
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* Setup new clockevent timer value.
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*/
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writel(delta, timer_base + TIMER1_VAL_OFF);
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/*
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* Enable the timer.
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*/
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u = readl(timer_base + TIMER_CTRL_OFF);
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u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
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writel(u, timer_base + TIMER_CTRL_OFF);
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local_irq_restore(flags);
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return 0;
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}
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static void
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orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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unsigned long flags;
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u32 u;
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local_irq_save(flags);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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/*
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* Setup timer to fire at 1/HZ intervals.
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*/
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writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
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writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
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/*
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* Enable timer interrupt.
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*/
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u = readl(bridge_base + BRIDGE_MASK_OFF);
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writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
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/*
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* Enable timer.
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*/
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u = readl(timer_base + TIMER_CTRL_OFF);
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writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
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timer_base + TIMER_CTRL_OFF);
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} else {
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/*
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* Disable timer.
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*/
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u = readl(timer_base + TIMER_CTRL_OFF);
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writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
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/*
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* Disable timer interrupt.
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*/
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u = readl(bridge_base + BRIDGE_MASK_OFF);
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writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
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/*
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* ACK pending timer interrupt.
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*/
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writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
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}
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local_irq_restore(flags);
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}
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static struct clock_event_device orion_clkevt = {
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.name = "orion_tick",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.shift = 32,
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.rating = 300,
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.set_next_event = orion_clkevt_next_event,
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.set_mode = orion_clkevt_mode,
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};
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static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
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{
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/*
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* ACK timer interrupt and call event handler.
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*/
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writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
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orion_clkevt.event_handler(&orion_clkevt);
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return IRQ_HANDLED;
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}
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static struct irqaction orion_timer_irq = {
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.name = "orion_tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = orion_timer_interrupt
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};
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void __init
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orion_time_set_base(u32 _timer_base)
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{
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timer_base = (void __iomem *)_timer_base;
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}
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void __init
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orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
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unsigned int irq, unsigned int tclk)
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{
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u32 u;
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/*
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* Set SoC-specific data.
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*/
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bridge_base = (void __iomem *)_bridge_base;
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bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
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ticks_per_jiffy = (tclk + HZ/2) / HZ;
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/*
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* Set scale and timer for sched_clock.
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*/
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setup_sched_clock(orion_read_sched_clock, 32, tclk);
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/*
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* Setup free-running clocksource timer (interrupts
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* disabled).
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*/
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writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
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writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
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u = readl(bridge_base + BRIDGE_MASK_OFF);
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writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
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u = readl(timer_base + TIMER_CTRL_OFF);
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writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
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clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
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tclk, 300, 32, clocksource_mmio_readl_down);
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/*
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* Setup clockevent timer (interrupt-driven).
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*/
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setup_irq(irq, &orion_timer_irq);
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orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
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orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
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orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
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orion_clkevt.cpumask = cpumask_of(0);
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clockevents_register_device(&orion_clkevt);
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}
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