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![Ashutosh Dixit](/assets/img/avatar_default.png)
HW allows arbitrary PL1 limits to be set but silently clamps these values to "typical but not guaranteed" min/max values in pkg_power_sku register. Follow the same pattern for sysfs, allow arbitrary PL1 limits to be set but display clamped values when read, so that users see PL1 limits HW is likely using. Otherwise users think HW is using arbitrarily high/low PL1 limits they might have set. The previous write/read I1 power1_crit limit also follows the same clamping pattern. v2: Explain "why" in commit message and include bug link (Jani Nikula) Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7704 Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221215191727.2468770-1-ashutosh.dixit@intel.com
763 lines
20 KiB
C
763 lines
20 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/types.h>
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#include "i915_drv.h"
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#include "i915_hwmon.h"
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#include "i915_reg.h"
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#include "intel_mchbar_regs.h"
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#include "intel_pcode.h"
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#include "gt/intel_gt.h"
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#include "gt/intel_gt_regs.h"
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/*
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* SF_* - scale factors for particular quantities according to hwmon spec.
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* - voltage - millivolts
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* - power - microwatts
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* - curr - milliamperes
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* - energy - microjoules
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* - time - milliseconds
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*/
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#define SF_VOLTAGE 1000
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#define SF_POWER 1000000
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#define SF_CURR 1000
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#define SF_ENERGY 1000000
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#define SF_TIME 1000
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struct hwm_reg {
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i915_reg_t gt_perf_status;
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i915_reg_t pkg_power_sku_unit;
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i915_reg_t pkg_power_sku;
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i915_reg_t pkg_rapl_limit;
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i915_reg_t energy_status_all;
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i915_reg_t energy_status_tile;
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};
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struct hwm_energy_info {
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u32 reg_val_prev;
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long accum_energy; /* Accumulated energy for energy1_input */
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};
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struct hwm_drvdata {
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struct i915_hwmon *hwmon;
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struct intel_uncore *uncore;
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struct device *hwmon_dev;
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struct hwm_energy_info ei; /* Energy info for energy1_input */
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char name[12];
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int gt_n;
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};
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struct i915_hwmon {
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struct hwm_drvdata ddat;
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struct hwm_drvdata ddat_gt[I915_MAX_GT];
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struct mutex hwmon_lock; /* counter overflow logic and rmw */
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struct hwm_reg rg;
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int scl_shift_power;
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int scl_shift_energy;
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int scl_shift_time;
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};
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static void
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hwm_locked_with_pm_intel_uncore_rmw(struct hwm_drvdata *ddat,
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i915_reg_t reg, u32 clear, u32 set)
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{
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struct i915_hwmon *hwmon = ddat->hwmon;
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struct intel_uncore *uncore = ddat->uncore;
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intel_wakeref_t wakeref;
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mutex_lock(&hwmon->hwmon_lock);
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with_intel_runtime_pm(uncore->rpm, wakeref)
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intel_uncore_rmw(uncore, reg, clear, set);
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mutex_unlock(&hwmon->hwmon_lock);
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}
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/*
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* This function's return type of u64 allows for the case where the scaling
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* of the field taken from the 32-bit register value might cause a result to
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* exceed 32 bits.
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*/
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static u64
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hwm_field_read_and_scale(struct hwm_drvdata *ddat, i915_reg_t rgadr,
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u32 field_msk, int nshift, u32 scale_factor)
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{
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struct intel_uncore *uncore = ddat->uncore;
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intel_wakeref_t wakeref;
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u32 reg_value;
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with_intel_runtime_pm(uncore->rpm, wakeref)
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reg_value = intel_uncore_read(uncore, rgadr);
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reg_value = REG_FIELD_GET(field_msk, reg_value);
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return mul_u64_u32_shr(reg_value, scale_factor, nshift);
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}
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static void
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hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
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int nshift, unsigned int scale_factor, long lval)
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{
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u32 nval;
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/* Computation in 64-bits to avoid overflow. Round to nearest. */
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nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
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hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
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PKG_PWR_LIM_1,
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REG_FIELD_PREP(PKG_PWR_LIM_1, nval));
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}
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/*
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* hwm_energy - Obtain energy value
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*
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* The underlying energy hardware register is 32-bits and is subject to
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* overflow. How long before overflow? For example, with an example
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* scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
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* a power draw of 1000 watts, the 32-bit counter will overflow in
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* approximately 4.36 minutes.
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*
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* Examples:
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* 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days
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* 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes
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*
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* The function significantly increases overflow duration (from 4.36
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* minutes) by accumulating the energy register into a 'long' as allowed by
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* the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
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* a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
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* hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
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* energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
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*/
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static void
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hwm_energy(struct hwm_drvdata *ddat, long *energy)
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{
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struct intel_uncore *uncore = ddat->uncore;
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struct i915_hwmon *hwmon = ddat->hwmon;
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struct hwm_energy_info *ei = &ddat->ei;
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intel_wakeref_t wakeref;
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i915_reg_t rgaddr;
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u32 reg_val;
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if (ddat->gt_n >= 0)
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rgaddr = hwmon->rg.energy_status_tile;
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else
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rgaddr = hwmon->rg.energy_status_all;
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mutex_lock(&hwmon->hwmon_lock);
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with_intel_runtime_pm(uncore->rpm, wakeref)
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reg_val = intel_uncore_read(uncore, rgaddr);
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if (reg_val >= ei->reg_val_prev)
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ei->accum_energy += reg_val - ei->reg_val_prev;
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else
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ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
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ei->reg_val_prev = reg_val;
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*energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
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hwmon->scl_shift_energy);
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mutex_unlock(&hwmon->hwmon_lock);
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}
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static ssize_t
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hwm_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct hwm_drvdata *ddat = dev_get_drvdata(dev);
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struct i915_hwmon *hwmon = ddat->hwmon;
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intel_wakeref_t wakeref;
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u32 r, x, y, x_w = 2; /* 2 bits */
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u64 tau4, out;
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with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
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r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit);
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x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
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y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
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/*
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* tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
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* = (4 | x) << (y - 2)
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* where (y - 2) ensures a 1.x fixed point representation of 1.x
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* However because y can be < 2, we compute
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* tau4 = (4 | x) << y
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* but add 2 when doing the final right shift to account for units
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*/
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tau4 = ((1 << x_w) | x) << y;
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/* val in hwmon interface units (millisec) */
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out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
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return sysfs_emit(buf, "%llu\n", out);
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}
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static ssize_t
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hwm_power1_max_interval_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct hwm_drvdata *ddat = dev_get_drvdata(dev);
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struct i915_hwmon *hwmon = ddat->hwmon;
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u32 x, y, rxy, x_w = 2; /* 2 bits */
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u64 tau4, r, max_win;
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unsigned long val;
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int ret;
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ret = kstrtoul(buf, 0, &val);
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if (ret)
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return ret;
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/*
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* Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12
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* The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds
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*/
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#define PKG_MAX_WIN_DEFAULT 0x12ull
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/*
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* val must be < max in hwmon interface units. The steps below are
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* explained in i915_power1_max_interval_show()
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*/
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r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
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x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
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y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
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tau4 = ((1 << x_w) | x) << y;
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max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
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if (val > max_win)
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return -EINVAL;
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/* val in hw units */
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val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
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/* Convert to 1.x * power(2,y) */
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if (!val)
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return -EINVAL;
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y = ilog2(val);
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/* x = (val - (1 << y)) >> (y - 2); */
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x = (val - (1ul << y)) << x_w >> y;
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rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
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hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit,
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PKG_PWR_LIM_1_TIME, rxy);
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return count;
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}
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static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
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hwm_power1_max_interval_show,
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hwm_power1_max_interval_store, 0);
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static struct attribute *hwm_attributes[] = {
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&sensor_dev_attr_power1_max_interval.dev_attr.attr,
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NULL
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};
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static umode_t hwm_attributes_visible(struct kobject *kobj,
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struct attribute *attr, int index)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct hwm_drvdata *ddat = dev_get_drvdata(dev);
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struct i915_hwmon *hwmon = ddat->hwmon;
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if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
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return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? attr->mode : 0;
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return 0;
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}
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static const struct attribute_group hwm_attrgroup = {
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.attrs = hwm_attributes,
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.is_visible = hwm_attributes_visible,
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};
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static const struct attribute_group *hwm_groups[] = {
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&hwm_attrgroup,
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NULL
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};
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static const struct hwmon_channel_info *hwm_info[] = {
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HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
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HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
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HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
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HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
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NULL
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};
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static const struct hwmon_channel_info *hwm_gt_info[] = {
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HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
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NULL
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};
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/* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
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static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval)
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{
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/* Avoid ILLEGAL_SUBCOMMAND "mailbox access failed" warning in snb_pcode_read */
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if (IS_DG1(i915) || IS_DG2(i915))
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return -ENXIO;
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return snb_pcode_read_p(&i915->uncore, PCODE_POWER_SETUP,
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POWER_SETUP_SUBCOMMAND_READ_I1, 0, uval);
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}
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static int hwm_pcode_write_i1(struct drm_i915_private *i915, u32 uval)
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{
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return snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
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POWER_SETUP_SUBCOMMAND_WRITE_I1, 0, uval);
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}
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static umode_t
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hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr)
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{
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struct drm_i915_private *i915 = ddat->uncore->i915;
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switch (attr) {
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case hwmon_in_input:
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return IS_DG1(i915) || IS_DG2(i915) ? 0444 : 0;
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default:
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return 0;
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}
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}
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static int
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hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
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{
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struct i915_hwmon *hwmon = ddat->hwmon;
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intel_wakeref_t wakeref;
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u32 reg_value;
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switch (attr) {
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case hwmon_in_input:
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with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
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reg_value = intel_uncore_read(ddat->uncore, hwmon->rg.gt_perf_status);
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/* HW register value in units of 2.5 millivolt */
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*val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10);
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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}
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static umode_t
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hwm_power_is_visible(const struct hwm_drvdata *ddat, u32 attr, int chan)
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{
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struct drm_i915_private *i915 = ddat->uncore->i915;
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struct i915_hwmon *hwmon = ddat->hwmon;
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u32 uval;
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switch (attr) {
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case hwmon_power_max:
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return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? 0664 : 0;
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case hwmon_power_rated_max:
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return i915_mmio_reg_valid(hwmon->rg.pkg_power_sku) ? 0444 : 0;
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case hwmon_power_crit:
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return (hwm_pcode_read_i1(i915, &uval) ||
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!(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
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default:
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return 0;
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}
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}
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/*
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* HW allows arbitrary PL1 limits to be set but silently clamps these values to
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* "typical but not guaranteed" min/max values in rg.pkg_power_sku. Follow the
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* same pattern for sysfs, allow arbitrary PL1 limits to be set but display
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* clamped values when read. Write/read I1 also follows the same pattern.
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*/
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static int
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hwm_power_max_read(struct hwm_drvdata *ddat, long *val)
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{
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struct i915_hwmon *hwmon = ddat->hwmon;
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intel_wakeref_t wakeref;
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u64 r, min, max;
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*val = hwm_field_read_and_scale(ddat,
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hwmon->rg.pkg_rapl_limit,
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PKG_PWR_LIM_1,
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hwmon->scl_shift_power,
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SF_POWER);
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with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
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r = intel_uncore_read64(ddat->uncore, hwmon->rg.pkg_power_sku);
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min = REG_FIELD_GET(PKG_MIN_PWR, r);
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min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
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max = REG_FIELD_GET(PKG_MAX_PWR, r);
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max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
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if (min && max)
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*val = clamp_t(u64, *val, min, max);
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return 0;
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}
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static int
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hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
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{
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struct i915_hwmon *hwmon = ddat->hwmon;
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int ret;
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u32 uval;
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switch (attr) {
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case hwmon_power_max:
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return hwm_power_max_read(ddat, val);
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case hwmon_power_rated_max:
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*val = hwm_field_read_and_scale(ddat,
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hwmon->rg.pkg_power_sku,
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PKG_PKG_TDP,
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hwmon->scl_shift_power,
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SF_POWER);
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return 0;
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case hwmon_power_crit:
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ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);
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if (ret)
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return ret;
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if (!(uval & POWER_SETUP_I1_WATTS))
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return -ENODEV;
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*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
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SF_POWER, POWER_SETUP_I1_SHIFT);
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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}
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static int
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hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
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{
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struct i915_hwmon *hwmon = ddat->hwmon;
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u32 uval;
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switch (attr) {
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case hwmon_power_max:
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hwm_field_scale_and_write(ddat,
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hwmon->rg.pkg_rapl_limit,
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hwmon->scl_shift_power,
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SF_POWER, val);
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return 0;
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case hwmon_power_crit:
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uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);
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return hwm_pcode_write_i1(ddat->uncore->i915, uval);
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|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static umode_t
|
|
hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)
|
|
{
|
|
struct i915_hwmon *hwmon = ddat->hwmon;
|
|
i915_reg_t rgaddr;
|
|
|
|
switch (attr) {
|
|
case hwmon_energy_input:
|
|
if (ddat->gt_n >= 0)
|
|
rgaddr = hwmon->rg.energy_status_tile;
|
|
else
|
|
rgaddr = hwmon->rg.energy_status_all;
|
|
return i915_mmio_reg_valid(rgaddr) ? 0444 : 0;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int
|
|
hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val)
|
|
{
|
|
switch (attr) {
|
|
case hwmon_energy_input:
|
|
hwm_energy(ddat, val);
|
|
return 0;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static umode_t
|
|
hwm_curr_is_visible(const struct hwm_drvdata *ddat, u32 attr)
|
|
{
|
|
struct drm_i915_private *i915 = ddat->uncore->i915;
|
|
u32 uval;
|
|
|
|
switch (attr) {
|
|
case hwmon_curr_crit:
|
|
return (hwm_pcode_read_i1(i915, &uval) ||
|
|
(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int
|
|
hwm_curr_read(struct hwm_drvdata *ddat, u32 attr, long *val)
|
|
{
|
|
int ret;
|
|
u32 uval;
|
|
|
|
switch (attr) {
|
|
case hwmon_curr_crit:
|
|
ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);
|
|
if (ret)
|
|
return ret;
|
|
if (uval & POWER_SETUP_I1_WATTS)
|
|
return -ENODEV;
|
|
*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
|
|
SF_CURR, POWER_SETUP_I1_SHIFT);
|
|
return 0;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static int
|
|
hwm_curr_write(struct hwm_drvdata *ddat, u32 attr, long val)
|
|
{
|
|
u32 uval;
|
|
|
|
switch (attr) {
|
|
case hwmon_curr_crit:
|
|
uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR);
|
|
return hwm_pcode_write_i1(ddat->uncore->i915, uval);
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static umode_t
|
|
hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
|
|
u32 attr, int channel)
|
|
{
|
|
struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata;
|
|
|
|
switch (type) {
|
|
case hwmon_in:
|
|
return hwm_in_is_visible(ddat, attr);
|
|
case hwmon_power:
|
|
return hwm_power_is_visible(ddat, attr, channel);
|
|
case hwmon_energy:
|
|
return hwm_energy_is_visible(ddat, attr);
|
|
case hwmon_curr:
|
|
return hwm_curr_is_visible(ddat, attr);
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int
|
|
hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
|
|
int channel, long *val)
|
|
{
|
|
struct hwm_drvdata *ddat = dev_get_drvdata(dev);
|
|
|
|
switch (type) {
|
|
case hwmon_in:
|
|
return hwm_in_read(ddat, attr, val);
|
|
case hwmon_power:
|
|
return hwm_power_read(ddat, attr, channel, val);
|
|
case hwmon_energy:
|
|
return hwm_energy_read(ddat, attr, val);
|
|
case hwmon_curr:
|
|
return hwm_curr_read(ddat, attr, val);
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static int
|
|
hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
|
|
int channel, long val)
|
|
{
|
|
struct hwm_drvdata *ddat = dev_get_drvdata(dev);
|
|
|
|
switch (type) {
|
|
case hwmon_power:
|
|
return hwm_power_write(ddat, attr, channel, val);
|
|
case hwmon_curr:
|
|
return hwm_curr_write(ddat, attr, val);
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static const struct hwmon_ops hwm_ops = {
|
|
.is_visible = hwm_is_visible,
|
|
.read = hwm_read,
|
|
.write = hwm_write,
|
|
};
|
|
|
|
static const struct hwmon_chip_info hwm_chip_info = {
|
|
.ops = &hwm_ops,
|
|
.info = hwm_info,
|
|
};
|
|
|
|
static umode_t
|
|
hwm_gt_is_visible(const void *drvdata, enum hwmon_sensor_types type,
|
|
u32 attr, int channel)
|
|
{
|
|
struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata;
|
|
|
|
switch (type) {
|
|
case hwmon_energy:
|
|
return hwm_energy_is_visible(ddat, attr);
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int
|
|
hwm_gt_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
|
|
int channel, long *val)
|
|
{
|
|
struct hwm_drvdata *ddat = dev_get_drvdata(dev);
|
|
|
|
switch (type) {
|
|
case hwmon_energy:
|
|
return hwm_energy_read(ddat, attr, val);
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static const struct hwmon_ops hwm_gt_ops = {
|
|
.is_visible = hwm_gt_is_visible,
|
|
.read = hwm_gt_read,
|
|
};
|
|
|
|
static const struct hwmon_chip_info hwm_gt_chip_info = {
|
|
.ops = &hwm_gt_ops,
|
|
.info = hwm_gt_info,
|
|
};
|
|
|
|
static void
|
|
hwm_get_preregistration_info(struct drm_i915_private *i915)
|
|
{
|
|
struct i915_hwmon *hwmon = i915->hwmon;
|
|
struct intel_uncore *uncore = &i915->uncore;
|
|
struct hwm_drvdata *ddat = &hwmon->ddat;
|
|
intel_wakeref_t wakeref;
|
|
u32 val_sku_unit = 0;
|
|
struct intel_gt *gt;
|
|
long energy;
|
|
int i;
|
|
|
|
/* Available for all Gen12+/dGfx */
|
|
hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
|
|
|
|
if (IS_DG1(i915) || IS_DG2(i915)) {
|
|
hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT;
|
|
hwmon->rg.pkg_power_sku = PCU_PACKAGE_POWER_SKU;
|
|
hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
|
|
hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
|
|
hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
|
|
} else if (IS_XEHPSDV(i915)) {
|
|
hwmon->rg.pkg_power_sku_unit = GT0_PACKAGE_POWER_SKU_UNIT;
|
|
hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
|
|
hwmon->rg.pkg_rapl_limit = GT0_PACKAGE_RAPL_LIMIT;
|
|
hwmon->rg.energy_status_all = GT0_PLATFORM_ENERGY_STATUS;
|
|
hwmon->rg.energy_status_tile = GT0_PACKAGE_ENERGY_STATUS;
|
|
} else {
|
|
hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
|
|
hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
|
|
hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;
|
|
hwmon->rg.energy_status_all = INVALID_MMIO_REG;
|
|
hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
|
|
}
|
|
|
|
with_intel_runtime_pm(uncore->rpm, wakeref) {
|
|
/*
|
|
* The contents of register hwmon->rg.pkg_power_sku_unit do not change,
|
|
* so read it once and store the shift values.
|
|
*/
|
|
if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku_unit))
|
|
val_sku_unit = intel_uncore_read(uncore,
|
|
hwmon->rg.pkg_power_sku_unit);
|
|
}
|
|
|
|
hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
|
|
hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
|
|
hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
|
|
|
|
/*
|
|
* Initialize 'struct hwm_energy_info', i.e. set fields to the
|
|
* first value of the energy register read
|
|
*/
|
|
if (i915_mmio_reg_valid(hwmon->rg.energy_status_all))
|
|
hwm_energy(ddat, &energy);
|
|
if (i915_mmio_reg_valid(hwmon->rg.energy_status_tile)) {
|
|
for_each_gt(gt, i915, i)
|
|
hwm_energy(&hwmon->ddat_gt[i], &energy);
|
|
}
|
|
}
|
|
|
|
void i915_hwmon_register(struct drm_i915_private *i915)
|
|
{
|
|
struct device *dev = i915->drm.dev;
|
|
struct i915_hwmon *hwmon;
|
|
struct device *hwmon_dev;
|
|
struct hwm_drvdata *ddat;
|
|
struct hwm_drvdata *ddat_gt;
|
|
struct intel_gt *gt;
|
|
int i;
|
|
|
|
/* hwmon is available only for dGfx */
|
|
if (!IS_DGFX(i915))
|
|
return;
|
|
|
|
hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
|
|
if (!hwmon)
|
|
return;
|
|
|
|
i915->hwmon = hwmon;
|
|
mutex_init(&hwmon->hwmon_lock);
|
|
ddat = &hwmon->ddat;
|
|
|
|
ddat->hwmon = hwmon;
|
|
ddat->uncore = &i915->uncore;
|
|
snprintf(ddat->name, sizeof(ddat->name), "i915");
|
|
ddat->gt_n = -1;
|
|
|
|
for_each_gt(gt, i915, i) {
|
|
ddat_gt = hwmon->ddat_gt + i;
|
|
|
|
ddat_gt->hwmon = hwmon;
|
|
ddat_gt->uncore = gt->uncore;
|
|
snprintf(ddat_gt->name, sizeof(ddat_gt->name), "i915_gt%u", i);
|
|
ddat_gt->gt_n = i;
|
|
}
|
|
|
|
hwm_get_preregistration_info(i915);
|
|
|
|
/* hwmon_dev points to device hwmon<i> */
|
|
hwmon_dev = devm_hwmon_device_register_with_info(dev, ddat->name,
|
|
ddat,
|
|
&hwm_chip_info,
|
|
hwm_groups);
|
|
if (IS_ERR(hwmon_dev)) {
|
|
i915->hwmon = NULL;
|
|
return;
|
|
}
|
|
|
|
ddat->hwmon_dev = hwmon_dev;
|
|
|
|
for_each_gt(gt, i915, i) {
|
|
ddat_gt = hwmon->ddat_gt + i;
|
|
/*
|
|
* Create per-gt directories only if a per-gt attribute is
|
|
* visible. Currently this is only energy
|
|
*/
|
|
if (!hwm_gt_is_visible(ddat_gt, hwmon_energy, hwmon_energy_input, 0))
|
|
continue;
|
|
|
|
hwmon_dev = devm_hwmon_device_register_with_info(dev, ddat_gt->name,
|
|
ddat_gt,
|
|
&hwm_gt_chip_info,
|
|
NULL);
|
|
if (!IS_ERR(hwmon_dev))
|
|
ddat_gt->hwmon_dev = hwmon_dev;
|
|
}
|
|
}
|
|
|
|
void i915_hwmon_unregister(struct drm_i915_private *i915)
|
|
{
|
|
fetch_and_zero(&i915->hwmon);
|
|
}
|