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![Tvrtko Ursulin](/assets/img/avatar_default.png)
Convert some usages of legacy DRM logging macros into versions which tell us on which device have the events occurred. v2: * Don't have struct drm_device as local. (Jani, Ville) v3: * Store gt, not i915, in workaround list. (John) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221109104633.2579245-1-tvrtko.ursulin@linux.intel.com
274 lines
7.2 KiB
C
274 lines
7.2 KiB
C
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Ben Widawsky <ben@bwidawsk.net>
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*
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/stat.h>
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#include <linux/sysfs.h>
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#include "gt/intel_gt_regs.h"
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#include "gt/intel_rc6.h"
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#include "gt/intel_rps.h"
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#include "gt/sysfs_engines.h"
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#include "i915_drv.h"
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#include "i915_sysfs.h"
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#include "intel_pm.h"
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struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
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{
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struct drm_minor *minor = dev_get_drvdata(kdev);
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return to_i915(minor->dev);
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}
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static int l3_access_valid(struct drm_i915_private *i915, loff_t offset)
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{
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if (!HAS_L3_DPF(i915))
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return -EPERM;
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if (!IS_ALIGNED(offset, sizeof(u32)))
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return -EINVAL;
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if (offset >= GEN7_L3LOG_SIZE)
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return -ENXIO;
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return 0;
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}
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static ssize_t
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i915_l3_read(struct file *filp, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t offset, size_t count)
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{
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struct device *kdev = kobj_to_dev(kobj);
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struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
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int slice = (int)(uintptr_t)attr->private;
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int ret;
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ret = l3_access_valid(i915, offset);
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if (ret)
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return ret;
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count = round_down(count, sizeof(u32));
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count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
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memset(buf, 0, count);
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spin_lock(&i915->gem.contexts.lock);
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if (i915->l3_parity.remap_info[slice])
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memcpy(buf,
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i915->l3_parity.remap_info[slice] + offset / sizeof(u32),
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count);
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spin_unlock(&i915->gem.contexts.lock);
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return count;
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}
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static ssize_t
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i915_l3_write(struct file *filp, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t offset, size_t count)
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{
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struct device *kdev = kobj_to_dev(kobj);
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struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
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int slice = (int)(uintptr_t)attr->private;
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u32 *remap_info, *freeme = NULL;
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struct i915_gem_context *ctx;
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int ret;
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ret = l3_access_valid(i915, offset);
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if (ret)
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return ret;
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if (count < sizeof(u32))
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return -EINVAL;
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remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
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if (!remap_info)
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return -ENOMEM;
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spin_lock(&i915->gem.contexts.lock);
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if (i915->l3_parity.remap_info[slice]) {
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freeme = remap_info;
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remap_info = i915->l3_parity.remap_info[slice];
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} else {
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i915->l3_parity.remap_info[slice] = remap_info;
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}
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count = round_down(count, sizeof(u32));
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memcpy(remap_info + offset / sizeof(u32), buf, count);
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/* NB: We defer the remapping until we switch to the context */
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list_for_each_entry(ctx, &i915->gem.contexts.list, link)
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ctx->remap_slice |= BIT(slice);
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spin_unlock(&i915->gem.contexts.lock);
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kfree(freeme);
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/*
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* TODO: Ideally we really want a GPU reset here to make sure errors
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* aren't propagated. Since I cannot find a stable way to reset the GPU
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* at this point it is left as a TODO.
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*/
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return count;
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}
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static const struct bin_attribute dpf_attrs = {
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.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
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.size = GEN7_L3LOG_SIZE,
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.read = i915_l3_read,
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.write = i915_l3_write,
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.mmap = NULL,
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.private = (void *)0
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};
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static const struct bin_attribute dpf_attrs_1 = {
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.attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
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.size = GEN7_L3LOG_SIZE,
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.read = i915_l3_read,
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.write = i915_l3_write,
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.mmap = NULL,
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.private = (void *)1
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};
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#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
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static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t off, size_t count)
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{
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struct device *kdev = kobj_to_dev(kobj);
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struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
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struct i915_gpu_coredump *gpu;
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ssize_t ret = 0;
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/*
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* FIXME: Concurrent clients triggering resets and reading + clearing
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* dumps can cause inconsistent sysfs reads when a user calls in with a
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* non-zero offset to complete a prior partial read but the
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* gpu_coredump has been cleared or replaced.
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*/
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gpu = i915_first_error_state(i915);
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if (IS_ERR(gpu)) {
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ret = PTR_ERR(gpu);
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} else if (gpu) {
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ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count);
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i915_gpu_coredump_put(gpu);
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} else {
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const char *str = "No error state collected\n";
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size_t len = strlen(str);
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if (off < len) {
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ret = min_t(size_t, count, len - off);
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memcpy(buf, str + off, ret);
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}
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}
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return ret;
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}
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static ssize_t error_state_write(struct file *file, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t off, size_t count)
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{
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struct device *kdev = kobj_to_dev(kobj);
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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drm_dbg(&dev_priv->drm, "Resetting error state\n");
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i915_reset_error_state(dev_priv);
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return count;
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}
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static const struct bin_attribute error_state_attr = {
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.attr.name = "error",
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.attr.mode = S_IRUSR | S_IWUSR,
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.size = 0,
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.read = error_state_read,
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.write = error_state_write,
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};
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static void i915_setup_error_capture(struct device *kdev)
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{
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if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
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drm_err(&kdev_minor_to_i915(kdev)->drm,
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"error_state sysfs setup failed\n");
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}
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static void i915_teardown_error_capture(struct device *kdev)
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{
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sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
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}
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#else
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static void i915_setup_error_capture(struct device *kdev) {}
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static void i915_teardown_error_capture(struct device *kdev) {}
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#endif
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void i915_setup_sysfs(struct drm_i915_private *dev_priv)
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{
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struct device *kdev = dev_priv->drm.primary->kdev;
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int ret;
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if (HAS_L3_DPF(dev_priv)) {
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ret = device_create_bin_file(kdev, &dpf_attrs);
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if (ret)
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drm_err(&dev_priv->drm,
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"l3 parity sysfs setup failed\n");
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if (NUM_L3_SLICES(dev_priv) > 1) {
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ret = device_create_bin_file(kdev,
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&dpf_attrs_1);
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if (ret)
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drm_err(&dev_priv->drm,
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"l3 parity slice 1 setup failed\n");
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}
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}
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dev_priv->sysfs_gt = kobject_create_and_add("gt", &kdev->kobj);
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if (!dev_priv->sysfs_gt)
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drm_warn(&dev_priv->drm,
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"failed to register GT sysfs directory\n");
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i915_setup_error_capture(kdev);
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intel_engines_add_sysfs(dev_priv);
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}
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void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
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{
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struct device *kdev = dev_priv->drm.primary->kdev;
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i915_teardown_error_capture(kdev);
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device_remove_bin_file(kdev, &dpf_attrs_1);
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device_remove_bin_file(kdev, &dpf_attrs);
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kobject_put(dev_priv->sysfs_gt);
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}
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