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0492a34c83
We use all kinds of weird names for our base address registers. Take the names from the spec and stick to them to avoid confusing everyone. The only exceptions are IOBAR and LMEMBAR since naming them IOBAR_BAR and LMEMBAR_BAR looks too funny, and yet I think that adding the _BAR to GTTMMADR & co. (which don't have one in the spec name) does make it more clear what they are. And IOBAR vs. GTTMMADR_BAR also looks a bit too inconsistent for my taste. v2: Fix gvt build v3: Add GEN2_IO_BAR for completeness Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221005195646.17201-1-ville.syrjala@linux.intel.com Acked-by: Matthew Auld <matthew.auld@intel.com>
110 lines
3.4 KiB
C
110 lines
3.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_PCI_CONFIG_H__
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#define __INTEL_PCI_CONFIG_H__
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/* PCI BARs */
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#define GEN2_GMADR_BAR 0
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#define GEN2_MMADR_BAR 1 /* MMIO+GTT, despite the name */
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#define GEN2_IO_BAR 2 /* 85x/865 */
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#define GEN3_MMADR_BAR 0 /* MMIO only */
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#define GEN3_IO_BAR 1
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#define GEN3_GMADR_BAR 2
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#define GEN3_GTTADR_BAR 3 /* GTT only */
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#define GEN4_GTTMMADR_BAR 0 /* MMIO+GTT */
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#define GEN4_GMADR_BAR 2
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#define GEN4_IO_BAR 4
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#define GEN12_LMEM_BAR 2
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static inline int intel_mmio_bar(int graphics_ver)
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{
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switch (graphics_ver) {
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case 2: return GEN2_MMADR_BAR;
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case 3: return GEN3_MMADR_BAR;
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default: return GEN4_GTTMMADR_BAR;
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}
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}
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/* BSM in include/drm/i915_drm.h */
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#define MCHBAR_I915 0x44
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#define MCHBAR_I965 0x48
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#define MCHBAR_SIZE (4 * 4096)
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#define DEVEN 0x54
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#define DEVEN_MCHBAR_EN (1 << 28)
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#define HPLLCC 0xc0 /* 85x only */
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#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
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#define GC_CLOCK_133_200 (0 << 0)
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#define GC_CLOCK_100_200 (1 << 0)
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#define GC_CLOCK_100_133 (2 << 0)
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#define GC_CLOCK_133_266 (3 << 0)
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#define GC_CLOCK_133_200_2 (4 << 0)
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#define GC_CLOCK_133_266_2 (5 << 0)
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#define GC_CLOCK_166_266 (6 << 0)
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#define GC_CLOCK_166_250 (7 << 0)
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#define I915_GDRST 0xc0
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#define GRDOM_FULL (0 << 2)
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#define GRDOM_RENDER (1 << 2)
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#define GRDOM_MEDIA (3 << 2)
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#define GRDOM_MASK (3 << 2)
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#define GRDOM_RESET_STATUS (1 << 1)
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#define GRDOM_RESET_ENABLE (1 << 0)
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/* BSpec only has register offset, PCI device and bit found empirically */
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#define I830_CLOCK_GATE 0xc8 /* device 0 */
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#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
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#define GCDGMBUS 0xcc
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#define GCFGC2 0xda
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#define GCFGC 0xf0 /* 915+ only */
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#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
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#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
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#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
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#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
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#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
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#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
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#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
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#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
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#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
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#define GC_DISPLAY_CLOCK_MASK (7 << 4)
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#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
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#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
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#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
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#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
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#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
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#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
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#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
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#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
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#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
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#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
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#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
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#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
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#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
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#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
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#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
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#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
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#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
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#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
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#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
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#define ASLE 0xe4
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#define ASLS 0xfc
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#define SWSCI 0xe8
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#define SWSCI_SCISEL (1 << 15)
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#define SWSCI_GSSCIE (1 << 0)
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/* legacy/combination backlight modes, also called LBB */
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#define LBPC 0xf4
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#endif /* __INTEL_PCI_CONFIG_H__ */
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