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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-14 06:35:12 +00:00
b26980ab2a
When inserting a SFP that runs at 2.5G, then the Serdes was still
configured to run at 1G. Because the config->speed was 0, and then the
speed of the serdes was not configured at all, it was using the default
value which is 1G. This patch stop calling the serdes function set_speed
and allow the serdes to figure out the speed based on the interface
type.
Fixes: d28d6d2e37 ("net: lan966x: add port module support")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
406 lines
12 KiB
C
406 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <linux/netdevice.h>
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#include <linux/phy/phy.h>
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#include "lan966x_main.h"
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/* Watermark encode */
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#define MULTIPLIER_BIT BIT(8)
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static u32 lan966x_wm_enc(u32 value)
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{
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value /= LAN966X_BUFFER_CELL_SZ;
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if (value >= MULTIPLIER_BIT) {
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value /= 16;
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if (value >= MULTIPLIER_BIT)
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value = (MULTIPLIER_BIT - 1);
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value |= MULTIPLIER_BIT;
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}
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return value;
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}
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static void lan966x_port_link_down(struct lan966x_port *port)
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{
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struct lan966x *lan966x = port->lan966x;
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u32 val, delay = 0;
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/* 0.5: Disable any AFI */
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lan_rmw(AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(1) |
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AFI_PORT_CFG_FRM_OUT_MAX_SET(0),
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AFI_PORT_CFG_FC_SKIP_TTI_INJ |
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AFI_PORT_CFG_FRM_OUT_MAX,
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lan966x, AFI_PORT_CFG(port->chip_port));
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/* wait for reg afi_port_frm_out to become 0 for the port */
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while (true) {
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val = lan_rd(lan966x, AFI_PORT_FRM_OUT(port->chip_port));
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if (!AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(val))
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break;
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usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
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delay++;
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if (delay == 2000) {
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pr_err("AFI timeout chip port %u", port->chip_port);
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break;
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}
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}
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delay = 0;
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/* 1: Reset the PCS Rx clock domain */
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lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(1),
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DEV_CLOCK_CFG_PCS_RX_RST,
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lan966x, DEV_CLOCK_CFG(port->chip_port));
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/* 2: Disable MAC frame reception */
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lan_rmw(DEV_MAC_ENA_CFG_RX_ENA_SET(0),
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DEV_MAC_ENA_CFG_RX_ENA,
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lan966x, DEV_MAC_ENA_CFG(port->chip_port));
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/* 3: Disable traffic being sent to or from switch port */
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lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0),
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QSYS_SW_PORT_MODE_PORT_ENA,
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lan966x, QSYS_SW_PORT_MODE(port->chip_port));
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/* 4: Disable dequeuing from the egress queues */
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lan_rmw(QSYS_PORT_MODE_DEQUEUE_DIS_SET(1),
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QSYS_PORT_MODE_DEQUEUE_DIS,
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lan966x, QSYS_PORT_MODE(port->chip_port));
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/* 5: Disable Flowcontrol */
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lan_rmw(SYS_PAUSE_CFG_PAUSE_ENA_SET(0),
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SYS_PAUSE_CFG_PAUSE_ENA,
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lan966x, SYS_PAUSE_CFG(port->chip_port));
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/* 5.1: Disable PFC */
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lan_rmw(QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(0),
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QSYS_SW_PORT_MODE_TX_PFC_ENA,
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lan966x, QSYS_SW_PORT_MODE(port->chip_port));
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/* 6: Wait a worst case time 8ms (jumbo/10Mbit) */
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usleep_range(8 * USEC_PER_MSEC, 9 * USEC_PER_MSEC);
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/* 7: Disable HDX backpressure */
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lan_rmw(SYS_FRONT_PORT_MODE_HDX_MODE_SET(0),
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SYS_FRONT_PORT_MODE_HDX_MODE,
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lan966x, SYS_FRONT_PORT_MODE(port->chip_port));
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/* 8: Flush the queues accociated with the port */
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lan_rmw(QSYS_SW_PORT_MODE_AGING_MODE_SET(3),
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QSYS_SW_PORT_MODE_AGING_MODE,
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lan966x, QSYS_SW_PORT_MODE(port->chip_port));
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/* 9: Enable dequeuing from the egress queues */
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lan_rmw(QSYS_PORT_MODE_DEQUEUE_DIS_SET(0),
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QSYS_PORT_MODE_DEQUEUE_DIS,
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lan966x, QSYS_PORT_MODE(port->chip_port));
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/* 10: Wait until flushing is complete */
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while (true) {
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val = lan_rd(lan966x, QSYS_SW_STATUS(port->chip_port));
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if (!QSYS_SW_STATUS_EQ_AVAIL_GET(val))
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break;
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usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
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delay++;
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if (delay == 2000) {
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pr_err("Flush timeout chip port %u", port->chip_port);
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break;
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}
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}
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/* 11: Reset the Port and MAC clock domains */
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lan_rmw(DEV_MAC_ENA_CFG_TX_ENA_SET(0),
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DEV_MAC_ENA_CFG_TX_ENA,
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lan966x, DEV_MAC_ENA_CFG(port->chip_port));
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lan_rmw(DEV_CLOCK_CFG_PORT_RST_SET(1),
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DEV_CLOCK_CFG_PORT_RST,
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lan966x, DEV_CLOCK_CFG(port->chip_port));
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usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
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lan_rmw(DEV_CLOCK_CFG_MAC_TX_RST_SET(1) |
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DEV_CLOCK_CFG_MAC_RX_RST_SET(1) |
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DEV_CLOCK_CFG_PORT_RST_SET(1),
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DEV_CLOCK_CFG_MAC_TX_RST |
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DEV_CLOCK_CFG_MAC_RX_RST |
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DEV_CLOCK_CFG_PORT_RST,
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lan966x, DEV_CLOCK_CFG(port->chip_port));
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/* 12: Clear flushing */
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lan_rmw(QSYS_SW_PORT_MODE_AGING_MODE_SET(2),
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QSYS_SW_PORT_MODE_AGING_MODE,
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lan966x, QSYS_SW_PORT_MODE(port->chip_port));
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/* The port is disabled and flushed, now set up the port in the
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* new operating mode
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*/
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}
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static void lan966x_port_link_up(struct lan966x_port *port)
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{
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struct lan966x_port_config *config = &port->config;
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struct lan966x *lan966x = port->lan966x;
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int speed = 0, mode = 0;
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int atop_wm = 0;
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switch (config->speed) {
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case SPEED_10:
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speed = LAN966X_SPEED_10;
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break;
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case SPEED_100:
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speed = LAN966X_SPEED_100;
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break;
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case SPEED_1000:
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speed = LAN966X_SPEED_1000;
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mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1);
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break;
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case SPEED_2500:
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speed = LAN966X_SPEED_2500;
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mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1);
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break;
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}
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/* Also the GIGA_MODE_ENA(1) needs to be set regardless of the
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* port speed for QSGMII ports.
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*/
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if (config->portmode == PHY_INTERFACE_MODE_QSGMII)
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mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1);
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lan_wr(config->duplex | mode,
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lan966x, DEV_MAC_MODE_CFG(port->chip_port));
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lan_rmw(DEV_MAC_IFG_CFG_TX_IFG_SET(config->duplex ? 6 : 5) |
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DEV_MAC_IFG_CFG_RX_IFG1_SET(config->speed == SPEED_10 ? 2 : 1) |
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DEV_MAC_IFG_CFG_RX_IFG2_SET(2),
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DEV_MAC_IFG_CFG_TX_IFG |
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DEV_MAC_IFG_CFG_RX_IFG1 |
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DEV_MAC_IFG_CFG_RX_IFG2,
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lan966x, DEV_MAC_IFG_CFG(port->chip_port));
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lan_rmw(DEV_MAC_HDX_CFG_SEED_SET(4) |
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DEV_MAC_HDX_CFG_SEED_LOAD_SET(1),
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DEV_MAC_HDX_CFG_SEED |
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DEV_MAC_HDX_CFG_SEED_LOAD,
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lan966x, DEV_MAC_HDX_CFG(port->chip_port));
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if (config->portmode == PHY_INTERFACE_MODE_GMII) {
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if (config->speed == SPEED_1000)
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lan_rmw(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(1),
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CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA,
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lan966x,
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CHIP_TOP_CUPHY_PORT_CFG(port->chip_port));
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else
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lan_rmw(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(0),
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CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA,
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lan966x,
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CHIP_TOP_CUPHY_PORT_CFG(port->chip_port));
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}
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/* No PFC */
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lan_wr(ANA_PFC_CFG_FC_LINK_SPEED_SET(speed),
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lan966x, ANA_PFC_CFG(port->chip_port));
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lan_rmw(DEV_PCS1G_CFG_PCS_ENA_SET(1),
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DEV_PCS1G_CFG_PCS_ENA,
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lan966x, DEV_PCS1G_CFG(port->chip_port));
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lan_rmw(DEV_PCS1G_SD_CFG_SD_ENA_SET(0),
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DEV_PCS1G_SD_CFG_SD_ENA,
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lan966x, DEV_PCS1G_SD_CFG(port->chip_port));
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/* Set Pause WM hysteresis, start/stop are in 1518 byte units */
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lan_wr(SYS_PAUSE_CFG_PAUSE_ENA_SET(1) |
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SYS_PAUSE_CFG_PAUSE_STOP_SET(lan966x_wm_enc(4 * 1518)) |
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SYS_PAUSE_CFG_PAUSE_START_SET(lan966x_wm_enc(6 * 1518)),
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lan966x, SYS_PAUSE_CFG(port->chip_port));
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/* Set SMAC of Pause frame (00:00:00:00:00:00) */
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lan_wr(0, lan966x, DEV_FC_MAC_LOW_CFG(port->chip_port));
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lan_wr(0, lan966x, DEV_FC_MAC_HIGH_CFG(port->chip_port));
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/* Flow control */
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lan_rmw(SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(speed) |
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SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(7) |
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SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(1) |
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SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(0xffff) |
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SYS_MAC_FC_CFG_RX_FC_ENA_SET(config->pause & MLO_PAUSE_RX ? 1 : 0) |
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SYS_MAC_FC_CFG_TX_FC_ENA_SET(config->pause & MLO_PAUSE_TX ? 1 : 0),
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SYS_MAC_FC_CFG_FC_LINK_SPEED |
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SYS_MAC_FC_CFG_FC_LATENCY_CFG |
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SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
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SYS_MAC_FC_CFG_PAUSE_VAL_CFG |
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SYS_MAC_FC_CFG_RX_FC_ENA |
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SYS_MAC_FC_CFG_TX_FC_ENA,
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lan966x, SYS_MAC_FC_CFG(port->chip_port));
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/* Tail dropping watermark */
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atop_wm = lan966x->shared_queue_sz;
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/* The total memory size is diveded by number of front ports plus CPU
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* port
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*/
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lan_wr(lan966x_wm_enc(atop_wm / lan966x->num_phys_ports + 1), lan966x,
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SYS_ATOP(port->chip_port));
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lan_wr(lan966x_wm_enc(atop_wm), lan966x, SYS_ATOP_TOT_CFG);
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/* This needs to be at the end */
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/* Enable MAC module */
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lan_wr(DEV_MAC_ENA_CFG_RX_ENA_SET(1) |
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DEV_MAC_ENA_CFG_TX_ENA_SET(1),
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lan966x, DEV_MAC_ENA_CFG(port->chip_port));
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/* Take out the clock from reset */
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lan_wr(DEV_CLOCK_CFG_LINK_SPEED_SET(speed),
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lan966x, DEV_CLOCK_CFG(port->chip_port));
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/* Core: Enable port for frame transfer */
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lan_wr(QSYS_SW_PORT_MODE_PORT_ENA_SET(1) |
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QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(1) |
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QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(1),
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lan966x, QSYS_SW_PORT_MODE(port->chip_port));
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lan_rmw(AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(0) |
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AFI_PORT_CFG_FRM_OUT_MAX_SET(16),
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AFI_PORT_CFG_FC_SKIP_TTI_INJ |
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AFI_PORT_CFG_FRM_OUT_MAX,
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lan966x, AFI_PORT_CFG(port->chip_port));
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}
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void lan966x_port_config_down(struct lan966x_port *port)
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{
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lan966x_port_link_down(port);
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}
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void lan966x_port_config_up(struct lan966x_port *port)
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{
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lan966x_port_link_up(port);
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}
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void lan966x_port_status_get(struct lan966x_port *port,
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struct phylink_link_state *state)
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{
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struct lan966x *lan966x = port->lan966x;
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bool link_down;
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u16 bmsr = 0;
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u16 lp_adv;
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u32 val;
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val = lan_rd(lan966x, DEV_PCS1G_STICKY(port->chip_port));
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link_down = DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(val);
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if (link_down)
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lan_wr(val, lan966x, DEV_PCS1G_STICKY(port->chip_port));
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/* Get both current Link and Sync status */
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val = lan_rd(lan966x, DEV_PCS1G_LINK_STATUS(port->chip_port));
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state->link = DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(val) &&
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DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(val);
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state->link &= !link_down;
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/* Get PCS ANEG status register */
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val = lan_rd(lan966x, DEV_PCS1G_ANEG_STATUS(port->chip_port));
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/* Aneg complete provides more information */
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if (DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(val)) {
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state->an_complete = true;
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bmsr |= state->link ? BMSR_LSTATUS : 0;
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bmsr |= BMSR_ANEGCOMPLETE;
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lp_adv = DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(val);
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phylink_mii_c22_pcs_decode_state(state, bmsr, lp_adv);
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} else {
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if (!state->link)
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return;
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if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
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state->speed = SPEED_1000;
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else if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
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state->speed = SPEED_2500;
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state->duplex = DUPLEX_FULL;
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}
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}
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int lan966x_port_pcs_set(struct lan966x_port *port,
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struct lan966x_port_config *config)
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{
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struct lan966x *lan966x = port->lan966x;
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bool inband_aneg = false;
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bool outband;
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if (config->inband) {
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if (config->portmode == PHY_INTERFACE_MODE_SGMII ||
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config->portmode == PHY_INTERFACE_MODE_QSGMII)
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inband_aneg = true; /* Cisco-SGMII in-band-aneg */
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else if (config->portmode == PHY_INTERFACE_MODE_1000BASEX &&
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config->autoneg)
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inband_aneg = true; /* Clause-37 in-band-aneg */
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outband = false;
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} else {
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outband = true;
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}
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/* Disable or enable inband */
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lan_rmw(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(outband),
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DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA,
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lan966x, DEV_PCS1G_MODE_CFG(port->chip_port));
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/* Enable PCS */
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lan_wr(DEV_PCS1G_CFG_PCS_ENA_SET(1),
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lan966x, DEV_PCS1G_CFG(port->chip_port));
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if (inband_aneg) {
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int adv = phylink_mii_c22_pcs_encode_advertisement(config->portmode,
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config->advertising);
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if (adv >= 0)
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/* Enable in-band aneg */
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lan_wr(DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(adv) |
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DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(1) |
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DEV_PCS1G_ANEG_CFG_ENA_SET(1) |
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DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(1),
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lan966x, DEV_PCS1G_ANEG_CFG(port->chip_port));
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} else {
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lan_wr(0, lan966x, DEV_PCS1G_ANEG_CFG(port->chip_port));
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}
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/* Take PCS out of reset */
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lan_rmw(DEV_CLOCK_CFG_LINK_SPEED_SET(2) |
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DEV_CLOCK_CFG_PCS_RX_RST_SET(0) |
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DEV_CLOCK_CFG_PCS_TX_RST_SET(0),
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DEV_CLOCK_CFG_LINK_SPEED |
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DEV_CLOCK_CFG_PCS_RX_RST |
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DEV_CLOCK_CFG_PCS_TX_RST,
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lan966x, DEV_CLOCK_CFG(port->chip_port));
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port->config = *config;
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return 0;
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}
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void lan966x_port_init(struct lan966x_port *port)
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{
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struct lan966x_port_config *config = &port->config;
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struct lan966x *lan966x = port->lan966x;
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lan_rmw(ANA_PORT_CFG_LEARN_ENA_SET(0),
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ANA_PORT_CFG_LEARN_ENA,
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lan966x, ANA_PORT_CFG(port->chip_port));
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lan966x_port_config_down(port);
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if (config->portmode != PHY_INTERFACE_MODE_QSGMII)
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return;
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lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(0) |
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DEV_CLOCK_CFG_PCS_TX_RST_SET(0) |
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DEV_CLOCK_CFG_LINK_SPEED_SET(LAN966X_SPEED_1000),
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DEV_CLOCK_CFG_PCS_RX_RST |
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DEV_CLOCK_CFG_PCS_TX_RST |
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DEV_CLOCK_CFG_LINK_SPEED,
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lan966x, DEV_CLOCK_CFG(port->chip_port));
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}
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