mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-29 23:53:32 +00:00
c658eac628
The Xtensa architecture allows to define custom instructions and registers. Registers that are bound to a coprocessor are only accessible if the corresponding enable bit is set, which allows to implement a 'lazy' context switch mechanism. Other registers needs to be saved and restore at the time of the context switch or during interrupt handling. This patch adds support for these additional states: - save and restore registers that are used by the compiler upon interrupt entry and exit. - context switch additional registers unbound to any coprocessor - 'lazy' context switch of registers bound to a coprocessor - ptrace interface to provide access to additional registers - update configuration files in include/asm-xtensa/variant-fsf Signed-off-by: Chris Zankel <chris@zankel.net>
28 lines
618 B
C
28 lines
618 B
C
/*
|
|
* include/asm-xtensa/sigcontext.h
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2001 - 2007 Tensilica Inc.
|
|
*/
|
|
|
|
#ifndef _XTENSA_SIGCONTEXT_H
|
|
#define _XTENSA_SIGCONTEXT_H
|
|
|
|
|
|
struct sigcontext {
|
|
unsigned long sc_pc;
|
|
unsigned long sc_ps;
|
|
unsigned long sc_lbeg;
|
|
unsigned long sc_lend;
|
|
unsigned long sc_lcount;
|
|
unsigned long sc_sar;
|
|
unsigned long sc_acclo;
|
|
unsigned long sc_acchi;
|
|
unsigned long sc_a[16];
|
|
void *sc_xtregs;
|
|
};
|
|
|
|
#endif /* _XTENSA_SIGCONTEXT_H */
|