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![Chris Wilson](/assets/img/avatar_default.png)
We currently capture the GPU state after we detect a hang. This is vital for us to both triage and debug hangs in the wild (post-mortem debugging). However, it comes at the cost of running some potentially dangerous code (since it has to make very few assumption about the state of the driver) that is quite resource intensive. This patch introduces both a method to disable error capture at runtime (for users who hit bugs at runtime and need a workaround) and to disable error capture at compiletime (for realtime users who want to minimise any possible latency, and never require error capture, saving ~30k of code). The cost is that we now have to be wary of (and test!) a kconfig flag and a module parameter. The effect of the module parameter is easy to verify through code inspection and runtime testing, but a kconfig flag needs regular compile checking. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch Link: http://patchwork.freedesktop.org/patch/msgid/20161012090522.367-2-chris@chris-wilson.co.uk
656 lines
18 KiB
C
656 lines
18 KiB
C
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Ben Widawsky <ben@bwidawsk.net>
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*
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/stat.h>
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#include <linux/sysfs.h>
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#include "intel_drv.h"
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#include "i915_drv.h"
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static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
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{
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struct drm_minor *minor = dev_get_drvdata(kdev);
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return to_i915(minor->dev);
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}
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#ifdef CONFIG_PM
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static u32 calc_residency(struct drm_i915_private *dev_priv,
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i915_reg_t reg)
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{
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u64 raw_time; /* 32b value may overflow during fixed point math */
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u64 units = 128ULL, div = 100000ULL;
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u32 ret;
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if (!intel_enable_rc6())
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return 0;
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intel_runtime_pm_get(dev_priv);
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/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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units = 1;
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div = dev_priv->czclk_freq;
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if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
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units <<= 8;
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} else if (IS_BROXTON(dev_priv)) {
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units = 1;
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div = 1200; /* 833.33ns */
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}
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raw_time = I915_READ(reg) * units;
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ret = DIV_ROUND_UP_ULL(raw_time, div);
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intel_runtime_pm_put(dev_priv);
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return ret;
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}
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static ssize_t
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show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6());
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}
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static ssize_t
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show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
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return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
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}
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static ssize_t
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show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
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return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
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}
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static ssize_t
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show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
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return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
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}
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static ssize_t
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show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
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return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
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}
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static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
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static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
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static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
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static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
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static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
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static struct attribute *rc6_attrs[] = {
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&dev_attr_rc6_enable.attr,
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&dev_attr_rc6_residency_ms.attr,
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NULL
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};
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static struct attribute_group rc6_attr_group = {
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.name = power_group_name,
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.attrs = rc6_attrs
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};
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static struct attribute *rc6p_attrs[] = {
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&dev_attr_rc6p_residency_ms.attr,
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&dev_attr_rc6pp_residency_ms.attr,
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NULL
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};
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static struct attribute_group rc6p_attr_group = {
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.name = power_group_name,
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.attrs = rc6p_attrs
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};
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static struct attribute *media_rc6_attrs[] = {
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&dev_attr_media_rc6_residency_ms.attr,
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NULL
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};
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static struct attribute_group media_rc6_attr_group = {
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.name = power_group_name,
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.attrs = media_rc6_attrs
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};
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#endif
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static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset)
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{
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if (!HAS_L3_DPF(dev_priv))
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return -EPERM;
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if (offset % 4 != 0)
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return -EINVAL;
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if (offset >= GEN7_L3LOG_SIZE)
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return -ENXIO;
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return 0;
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}
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static ssize_t
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i915_l3_read(struct file *filp, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t offset, size_t count)
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{
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struct device *kdev = kobj_to_dev(kobj);
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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struct drm_device *dev = &dev_priv->drm;
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int slice = (int)(uintptr_t)attr->private;
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int ret;
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count = round_down(count, 4);
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ret = l3_access_valid(dev_priv, offset);
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if (ret)
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return ret;
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count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
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ret = i915_mutex_lock_interruptible(dev);
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if (ret)
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return ret;
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if (dev_priv->l3_parity.remap_info[slice])
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memcpy(buf,
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dev_priv->l3_parity.remap_info[slice] + (offset/4),
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count);
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else
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memset(buf, 0, count);
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mutex_unlock(&dev->struct_mutex);
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return count;
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}
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static ssize_t
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i915_l3_write(struct file *filp, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t offset, size_t count)
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{
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struct device *kdev = kobj_to_dev(kobj);
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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struct drm_device *dev = &dev_priv->drm;
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struct i915_gem_context *ctx;
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u32 *temp = NULL; /* Just here to make handling failures easy */
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int slice = (int)(uintptr_t)attr->private;
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int ret;
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if (!HAS_HW_CONTEXTS(dev_priv))
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return -ENXIO;
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ret = l3_access_valid(dev_priv, offset);
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if (ret)
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return ret;
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ret = i915_mutex_lock_interruptible(dev);
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if (ret)
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return ret;
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if (!dev_priv->l3_parity.remap_info[slice]) {
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temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
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if (!temp) {
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mutex_unlock(&dev->struct_mutex);
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return -ENOMEM;
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}
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}
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/* TODO: Ideally we really want a GPU reset here to make sure errors
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* aren't propagated. Since I cannot find a stable way to reset the GPU
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* at this point it is left as a TODO.
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*/
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if (temp)
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dev_priv->l3_parity.remap_info[slice] = temp;
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memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
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/* NB: We defer the remapping until we switch to the context */
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list_for_each_entry(ctx, &dev_priv->context_list, link)
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ctx->remap_slice |= (1<<slice);
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mutex_unlock(&dev->struct_mutex);
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return count;
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}
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static struct bin_attribute dpf_attrs = {
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.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
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.size = GEN7_L3LOG_SIZE,
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.read = i915_l3_read,
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.write = i915_l3_write,
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.mmap = NULL,
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.private = (void *)0
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};
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static struct bin_attribute dpf_attrs_1 = {
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.attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
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.size = GEN7_L3LOG_SIZE,
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.read = i915_l3_read,
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.write = i915_l3_write,
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.mmap = NULL,
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.private = (void *)1
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};
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static ssize_t gt_act_freq_mhz_show(struct device *kdev,
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struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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int ret;
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intel_runtime_pm_get(dev_priv);
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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u32 freq;
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freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
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ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
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} else {
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u32 rpstat = I915_READ(GEN6_RPSTAT1);
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if (IS_GEN9(dev_priv))
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ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
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else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
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else
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ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
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ret = intel_gpu_freq(dev_priv, ret);
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}
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mutex_unlock(&dev_priv->rps.hw_lock);
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intel_runtime_pm_put(dev_priv);
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return snprintf(buf, PAGE_SIZE, "%d\n", ret);
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}
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static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
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struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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return snprintf(buf, PAGE_SIZE, "%d\n",
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intel_gpu_freq(dev_priv,
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dev_priv->rps.cur_freq));
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}
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static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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return snprintf(buf, PAGE_SIZE, "%d\n",
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intel_gpu_freq(dev_priv,
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dev_priv->rps.boost_freq));
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}
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static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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u32 val;
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ssize_t ret;
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ret = kstrtou32(buf, 0, &val);
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if (ret)
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return ret;
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/* Validate against (static) hardware limits */
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val = intel_freq_opcode(dev_priv, val);
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if (val < dev_priv->rps.min_freq || val > dev_priv->rps.max_freq)
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return -EINVAL;
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mutex_lock(&dev_priv->rps.hw_lock);
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dev_priv->rps.boost_freq = val;
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mutex_unlock(&dev_priv->rps.hw_lock);
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return count;
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}
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static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
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struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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return snprintf(buf, PAGE_SIZE, "%d\n",
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intel_gpu_freq(dev_priv,
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dev_priv->rps.efficient_freq));
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}
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static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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return snprintf(buf, PAGE_SIZE, "%d\n",
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intel_gpu_freq(dev_priv,
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dev_priv->rps.max_freq_softlimit));
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}
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static ssize_t gt_max_freq_mhz_store(struct device *kdev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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u32 val;
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ssize_t ret;
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ret = kstrtou32(buf, 0, &val);
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if (ret)
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return ret;
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intel_runtime_pm_get(dev_priv);
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mutex_lock(&dev_priv->rps.hw_lock);
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val = intel_freq_opcode(dev_priv, val);
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if (val < dev_priv->rps.min_freq ||
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val > dev_priv->rps.max_freq ||
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val < dev_priv->rps.min_freq_softlimit) {
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mutex_unlock(&dev_priv->rps.hw_lock);
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intel_runtime_pm_put(dev_priv);
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return -EINVAL;
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}
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if (val > dev_priv->rps.rp0_freq)
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DRM_DEBUG("User requested overclocking to %d\n",
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intel_gpu_freq(dev_priv, val));
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dev_priv->rps.max_freq_softlimit = val;
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val = clamp_t(int, dev_priv->rps.cur_freq,
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dev_priv->rps.min_freq_softlimit,
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dev_priv->rps.max_freq_softlimit);
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/* We still need *_set_rps to process the new max_delay and
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* update the interrupt limits and PMINTRMSK even though
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* frequency request may be unchanged. */
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intel_set_rps(dev_priv, val);
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mutex_unlock(&dev_priv->rps.hw_lock);
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intel_runtime_pm_put(dev_priv);
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return count;
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}
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static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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return snprintf(buf, PAGE_SIZE, "%d\n",
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intel_gpu_freq(dev_priv,
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dev_priv->rps.min_freq_softlimit));
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}
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static ssize_t gt_min_freq_mhz_store(struct device *kdev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
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u32 val;
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ssize_t ret;
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ret = kstrtou32(buf, 0, &val);
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if (ret)
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return ret;
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intel_runtime_pm_get(dev_priv);
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mutex_lock(&dev_priv->rps.hw_lock);
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val = intel_freq_opcode(dev_priv, val);
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if (val < dev_priv->rps.min_freq ||
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val > dev_priv->rps.max_freq ||
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val > dev_priv->rps.max_freq_softlimit) {
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mutex_unlock(&dev_priv->rps.hw_lock);
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intel_runtime_pm_put(dev_priv);
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return -EINVAL;
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}
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dev_priv->rps.min_freq_softlimit = val;
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val = clamp_t(int, dev_priv->rps.cur_freq,
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dev_priv->rps.min_freq_softlimit,
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dev_priv->rps.max_freq_softlimit);
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/* We still need *_set_rps to process the new min_delay and
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* update the interrupt limits and PMINTRMSK even though
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* frequency request may be unchanged. */
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intel_set_rps(dev_priv, val);
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mutex_unlock(&dev_priv->rps.hw_lock);
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intel_runtime_pm_put(dev_priv);
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return count;
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}
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static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
|
|
static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
|
|
static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store);
|
|
static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
|
|
static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
|
|
|
|
static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
|
|
|
|
static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
|
|
static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
|
|
static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
|
|
static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
|
|
|
|
/* For now we have a static number of RP states */
|
|
static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
|
|
{
|
|
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
|
|
u32 val;
|
|
|
|
if (attr == &dev_attr_gt_RP0_freq_mhz)
|
|
val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
|
|
else if (attr == &dev_attr_gt_RP1_freq_mhz)
|
|
val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
|
|
else if (attr == &dev_attr_gt_RPn_freq_mhz)
|
|
val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
|
|
else
|
|
BUG();
|
|
|
|
return snprintf(buf, PAGE_SIZE, "%d\n", val);
|
|
}
|
|
|
|
static const struct attribute *gen6_attrs[] = {
|
|
&dev_attr_gt_act_freq_mhz.attr,
|
|
&dev_attr_gt_cur_freq_mhz.attr,
|
|
&dev_attr_gt_boost_freq_mhz.attr,
|
|
&dev_attr_gt_max_freq_mhz.attr,
|
|
&dev_attr_gt_min_freq_mhz.attr,
|
|
&dev_attr_gt_RP0_freq_mhz.attr,
|
|
&dev_attr_gt_RP1_freq_mhz.attr,
|
|
&dev_attr_gt_RPn_freq_mhz.attr,
|
|
NULL,
|
|
};
|
|
|
|
static const struct attribute *vlv_attrs[] = {
|
|
&dev_attr_gt_act_freq_mhz.attr,
|
|
&dev_attr_gt_cur_freq_mhz.attr,
|
|
&dev_attr_gt_boost_freq_mhz.attr,
|
|
&dev_attr_gt_max_freq_mhz.attr,
|
|
&dev_attr_gt_min_freq_mhz.attr,
|
|
&dev_attr_gt_RP0_freq_mhz.attr,
|
|
&dev_attr_gt_RP1_freq_mhz.attr,
|
|
&dev_attr_gt_RPn_freq_mhz.attr,
|
|
&dev_attr_vlv_rpe_freq_mhz.attr,
|
|
NULL,
|
|
};
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
|
|
|
|
static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
|
|
struct bin_attribute *attr, char *buf,
|
|
loff_t off, size_t count)
|
|
{
|
|
|
|
struct device *kdev = kobj_to_dev(kobj);
|
|
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
|
|
struct drm_device *dev = &dev_priv->drm;
|
|
struct i915_error_state_file_priv error_priv;
|
|
struct drm_i915_error_state_buf error_str;
|
|
ssize_t ret_count = 0;
|
|
int ret;
|
|
|
|
memset(&error_priv, 0, sizeof(error_priv));
|
|
|
|
ret = i915_error_state_buf_init(&error_str, to_i915(dev), count, off);
|
|
if (ret)
|
|
return ret;
|
|
|
|
error_priv.dev = dev;
|
|
i915_error_state_get(dev, &error_priv);
|
|
|
|
ret = i915_error_state_to_str(&error_str, &error_priv);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret_count = count < error_str.bytes ? count : error_str.bytes;
|
|
|
|
memcpy(buf, error_str.buf, ret_count);
|
|
out:
|
|
i915_error_state_put(&error_priv);
|
|
i915_error_state_buf_release(&error_str);
|
|
|
|
return ret ?: ret_count;
|
|
}
|
|
|
|
static ssize_t error_state_write(struct file *file, struct kobject *kobj,
|
|
struct bin_attribute *attr, char *buf,
|
|
loff_t off, size_t count)
|
|
{
|
|
struct device *kdev = kobj_to_dev(kobj);
|
|
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
|
|
|
|
DRM_DEBUG_DRIVER("Resetting error state\n");
|
|
i915_destroy_error_state(&dev_priv->drm);
|
|
|
|
return count;
|
|
}
|
|
|
|
static struct bin_attribute error_state_attr = {
|
|
.attr.name = "error",
|
|
.attr.mode = S_IRUSR | S_IWUSR,
|
|
.size = 0,
|
|
.read = error_state_read,
|
|
.write = error_state_write,
|
|
};
|
|
|
|
static void i915_setup_error_capture(struct device *kdev)
|
|
{
|
|
if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
|
|
DRM_ERROR("error_state sysfs setup failed\n");
|
|
}
|
|
|
|
static void i915_teardown_error_capture(struct device *kdev)
|
|
{
|
|
sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
|
|
}
|
|
#else
|
|
static void i915_setup_error_capture(struct device *kdev) {}
|
|
static void i915_teardown_error_capture(struct device *kdev) {}
|
|
#endif
|
|
|
|
void i915_setup_sysfs(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct device *kdev = dev_priv->drm.primary->kdev;
|
|
int ret;
|
|
|
|
#ifdef CONFIG_PM
|
|
if (HAS_RC6(dev_priv)) {
|
|
ret = sysfs_merge_group(&kdev->kobj,
|
|
&rc6_attr_group);
|
|
if (ret)
|
|
DRM_ERROR("RC6 residency sysfs setup failed\n");
|
|
}
|
|
if (HAS_RC6p(dev_priv)) {
|
|
ret = sysfs_merge_group(&kdev->kobj,
|
|
&rc6p_attr_group);
|
|
if (ret)
|
|
DRM_ERROR("RC6p residency sysfs setup failed\n");
|
|
}
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
|
ret = sysfs_merge_group(&kdev->kobj,
|
|
&media_rc6_attr_group);
|
|
if (ret)
|
|
DRM_ERROR("Media RC6 residency sysfs setup failed\n");
|
|
}
|
|
#endif
|
|
if (HAS_L3_DPF(dev_priv)) {
|
|
ret = device_create_bin_file(kdev, &dpf_attrs);
|
|
if (ret)
|
|
DRM_ERROR("l3 parity sysfs setup failed\n");
|
|
|
|
if (NUM_L3_SLICES(dev_priv) > 1) {
|
|
ret = device_create_bin_file(kdev,
|
|
&dpf_attrs_1);
|
|
if (ret)
|
|
DRM_ERROR("l3 parity slice 1 setup failed\n");
|
|
}
|
|
}
|
|
|
|
ret = 0;
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
|
|
else if (INTEL_GEN(dev_priv) >= 6)
|
|
ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
|
|
if (ret)
|
|
DRM_ERROR("RPS sysfs setup failed\n");
|
|
|
|
i915_setup_error_capture(kdev);
|
|
}
|
|
|
|
void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct device *kdev = dev_priv->drm.primary->kdev;
|
|
|
|
i915_teardown_error_capture(kdev);
|
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
sysfs_remove_files(&kdev->kobj, vlv_attrs);
|
|
else
|
|
sysfs_remove_files(&kdev->kobj, gen6_attrs);
|
|
device_remove_bin_file(kdev, &dpf_attrs_1);
|
|
device_remove_bin_file(kdev, &dpf_attrs);
|
|
#ifdef CONFIG_PM
|
|
sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
|
|
sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
|
|
#endif
|
|
}
|