mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 13:53:33 +00:00
4faf31b434
Now that the internals of mailbox operations are abstracted from the PCI specifics a bulk of infrastructure can move to the core. The CXL_PMEM driver intends to proxy LIBNVDIMM UAPI and driver requests to the equivalent functionality provided by the CXL hardware mailbox interface. In support of that intent move the mailbox implementation to a shared location for the CXL_PCI driver native IOCTL path and CXL_PMEM nvdimm command proxy path to share. A unit test framework seeks to implement a unit test backend transport for mailbox commands to communicate mocked up payloads. It can reuse all of the mailbox infrastructure minus the PCI specifics, so that also gets moved to the core. Finally with the mailbox infrastructure and ioctl handling being transport generic there is no longer any need to pass file file_operations to devm_cxl_add_memdev(). That allows all the ioctl boilerplate to move into the core for unit test reuse. No functional change intended, just code movement. Acked-by: Ben Widawsky <ben.widawsky@intel.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/163116435233.2460985.16197340449713287180.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
61 lines
1.5 KiB
ReStructuredText
61 lines
1.5 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
|
|
.. include:: <isonum.txt>
|
|
|
|
===================================
|
|
Compute Express Link Memory Devices
|
|
===================================
|
|
|
|
A Compute Express Link Memory Device is a CXL component that implements the
|
|
CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
|
|
or both. It is enumerated as a PCI device for configuration and passing
|
|
messages over an MMIO mailbox. Its contribution to the System Physical
|
|
Address space is handled via HDM (Host Managed Device Memory) decoders
|
|
that optionally define a device's contribution to an interleaved address
|
|
range across multiple devices underneath a host-bridge or interleaved
|
|
across host-bridges.
|
|
|
|
Driver Infrastructure
|
|
=====================
|
|
|
|
This section covers the driver infrastructure for a CXL memory device.
|
|
|
|
CXL Memory Device
|
|
-----------------
|
|
|
|
.. kernel-doc:: drivers/cxl/pci.c
|
|
:doc: cxl pci
|
|
|
|
.. kernel-doc:: drivers/cxl/pci.c
|
|
:internal:
|
|
|
|
CXL Core
|
|
--------
|
|
.. kernel-doc:: drivers/cxl/cxl.h
|
|
:doc: cxl objects
|
|
|
|
.. kernel-doc:: drivers/cxl/cxl.h
|
|
:internal:
|
|
|
|
.. kernel-doc:: drivers/cxl/core/bus.c
|
|
:doc: cxl core
|
|
|
|
.. kernel-doc:: drivers/cxl/core/pmem.c
|
|
:doc: cxl pmem
|
|
|
|
.. kernel-doc:: drivers/cxl/core/regs.c
|
|
:doc: cxl registers
|
|
|
|
.. kernel-doc:: drivers/cxl/core/mbox.c
|
|
:doc: cxl mbox
|
|
|
|
External Interfaces
|
|
===================
|
|
|
|
CXL IOCTL Interface
|
|
-------------------
|
|
|
|
.. kernel-doc:: include/uapi/linux/cxl_mem.h
|
|
:doc: UAPI
|
|
|
|
.. kernel-doc:: include/uapi/linux/cxl_mem.h
|
|
:internal:
|