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ARM Performance Monitoring Unit Table describes the properties of PMU support in ARM-based system. The APMT table contains a list of nodes, each represents a PMU in the system that conforms to ARM CoreSight PMU architecture. The properties of each node include information required to access the PMU (e.g. MMIO base address, interrupt number) and also identification. For more detailed information, please refer to the specification below: * APMT: https://developer.arm.com/documentation/den0117/latest * ARM Coresight PMU: https://developer.arm.com/documentation/ihi0091/latest The initial support adds the detection of APMT table and generic infrastructure to create platform devices for ARM CoreSight PMUs. Similar to IORT the root pointer of APMT is preserved during runtime and each PMU platform device is given a pointer to the corresponding APMT node. Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Link: https://lore.kernel.org/r/20220929002834.32664-1-bwicaksono@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
19 lines
367 B
C
19 lines
367 B
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* ARM CoreSight PMU driver.
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES.
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*
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*/
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#ifndef __ACPI_APMT_H__
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#define __ACPI_APMT_H__
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#include <linux/acpi.h>
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#ifdef CONFIG_ACPI_APMT
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void acpi_apmt_init(void);
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#else
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static inline void acpi_apmt_init(void) { }
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#endif /* CONFIG_ACPI_APMT */
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#endif /* __ACPI_APMT_H__ */
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