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ddec3bdee0
acpi_os_get_root_pointer() may return a valid address even if acpi_disabled
is set, but the host bridge information from the ACPI tables is not going
to be used in that case and the Broadcom host bridge initialization should
not be skipped then, So make broadcom_postcore_init() check acpi_disabled
too to avoid this issue.
Fixes: 6361d72b04 (x86/PCI: read Broadcom CNB20LE host bridge info before PCI scan)
Reported-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Linux PCI <linux-pci@vger.kernel.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/3186627.pxZj1QbYNg@aspire.rjw.lan
Signed-off-by: Ingo Molnar <mingo@kernel.org>
116 lines
3.3 KiB
C
116 lines
3.3 KiB
C
/*
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* Read address ranges from a Broadcom CNB20LE Host Bridge
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*
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* Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/dmi.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/pci_x86.h>
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#include <asm/pci-direct.h>
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#include "bus_numa.h"
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static void __init cnb20le_res(u8 bus, u8 slot, u8 func)
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{
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struct pci_root_info *info;
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struct pci_root_res *root_res;
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struct resource res;
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u16 word1, word2;
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u8 fbus, lbus;
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/* read the PCI bus numbers */
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fbus = read_pci_config_byte(bus, slot, func, 0x44);
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lbus = read_pci_config_byte(bus, slot, func, 0x45);
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info = alloc_pci_root_info(fbus, lbus, 0, 0);
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/*
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* Add the legacy IDE ports on bus 0
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*
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* These do not exist anywhere in the bridge registers, AFAICT. I do
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* not have the datasheet, so this is the best I can do.
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*/
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if (fbus == 0) {
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update_res(info, 0x01f0, 0x01f7, IORESOURCE_IO, 0);
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update_res(info, 0x03f6, 0x03f6, IORESOURCE_IO, 0);
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update_res(info, 0x0170, 0x0177, IORESOURCE_IO, 0);
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update_res(info, 0x0376, 0x0376, IORESOURCE_IO, 0);
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update_res(info, 0xffa0, 0xffaf, IORESOURCE_IO, 0);
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}
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/* read the non-prefetchable memory window */
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word1 = read_pci_config_16(bus, slot, func, 0xc0);
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word2 = read_pci_config_16(bus, slot, func, 0xc2);
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if (word1 != word2) {
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res.start = (word1 << 16) | 0x0000;
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res.end = (word2 << 16) | 0xffff;
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res.flags = IORESOURCE_MEM;
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update_res(info, res.start, res.end, res.flags, 0);
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}
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/* read the prefetchable memory window */
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word1 = read_pci_config_16(bus, slot, func, 0xc4);
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word2 = read_pci_config_16(bus, slot, func, 0xc6);
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if (word1 != word2) {
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res.start = ((resource_size_t) word1 << 16) | 0x0000;
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res.end = ((resource_size_t) word2 << 16) | 0xffff;
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res.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
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update_res(info, res.start, res.end, res.flags, 0);
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}
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/* read the IO port window */
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word1 = read_pci_config_16(bus, slot, func, 0xd0);
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word2 = read_pci_config_16(bus, slot, func, 0xd2);
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if (word1 != word2) {
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res.start = word1;
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res.end = word2;
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res.flags = IORESOURCE_IO;
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update_res(info, res.start, res.end, res.flags, 0);
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}
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/* print information about this host bridge */
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res.start = fbus;
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res.end = lbus;
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res.flags = IORESOURCE_BUS;
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printk(KERN_INFO "CNB20LE PCI Host Bridge (domain 0000 %pR)\n", &res);
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list_for_each_entry(root_res, &info->resources, list)
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printk(KERN_INFO "host bridge window %pR\n", &root_res->res);
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}
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static int __init broadcom_postcore_init(void)
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{
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u8 bus = 0, slot = 0;
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u32 id;
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u16 vendor, device;
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#ifdef CONFIG_ACPI
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/*
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* We should get host bridge information from ACPI unless the BIOS
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* doesn't support it.
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*/
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if (!acpi_disabled && acpi_os_get_root_pointer())
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return 0;
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#endif
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id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
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vendor = id & 0xffff;
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device = (id >> 16) & 0xffff;
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if (vendor == PCI_VENDOR_ID_SERVERWORKS &&
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device == PCI_DEVICE_ID_SERVERWORKS_LE) {
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cnb20le_res(bus, slot, 0);
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cnb20le_res(bus, slot, 1);
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}
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return 0;
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}
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postcore_initcall(broadcom_postcore_init);
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