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2a8a0f420f
The nest MMU in POWER9 does not re-fetch the PTE in response to
permission mismatch, contrary to the architecture[*] and unlike the core
MMU. This requires a TLB flush before upgrading permissions of valid
PTEs, for any address space with a coprocessor attached.
Per (non-public) Nest MMU Workbook, POWER10 nest MMU conforms to the
architecture in this regard, so skip the workaround.
[*] See: Power ISA Version 3.1B, 6.10.1.2 Modifying a Translation Table
Entry, Setting a Reference or Change Bit or Upgrading Access
Authority (PTE Subject to Atomic Hardware Updates):
"If the only change being made to a valid PTE that is subject to
atomic hardware updates is to set the Reference or Change bit to
1 or to upgrade access authority, a simpler sequence suffices
because the translation hardware will refetch the PTE if an
access is attempted for which the only problems were reference
and/or change bits needing to be set or insufficient access
authority."
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220525022358.780745-3-npiggin@gmail.com
61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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#include <linux/security.h>
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#include <asm/cacheflush.h>
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#include <asm/machdep.h>
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#include <asm/mman.h>
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#include <asm/tlb.h>
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void radix__flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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int psize;
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struct hstate *hstate = hstate_file(vma->vm_file);
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psize = hstate_get_psize(hstate);
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radix__flush_tlb_page_psize(vma->vm_mm, vmaddr, psize);
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}
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void radix__local_flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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int psize;
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struct hstate *hstate = hstate_file(vma->vm_file);
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psize = hstate_get_psize(hstate);
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radix__local_flush_tlb_page_psize(vma->vm_mm, vmaddr, psize);
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}
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void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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int psize;
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struct hstate *hstate = hstate_file(vma->vm_file);
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psize = hstate_get_psize(hstate);
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/*
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* Flush PWC even if we get PUD_SIZE hugetlb invalidate to keep this simpler.
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*/
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if (end - start >= PUD_SIZE)
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radix__flush_tlb_pwc_range_psize(vma->vm_mm, start, end, psize);
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else
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radix__flush_tlb_range_psize(vma->vm_mm, start, end, psize);
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}
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void radix__huge_ptep_modify_prot_commit(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep,
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pte_t old_pte, pte_t pte)
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{
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struct mm_struct *mm = vma->vm_mm;
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/*
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* POWER9 NMMU must flush the TLB after clearing the PTE before
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* installing a PTE with more relaxed access permissions, see
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* radix__ptep_set_access_flags.
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*/
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if (!cpu_has_feature(CPU_FTR_ARCH_31) &&
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is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) &&
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atomic_read(&mm->context.copros) > 0)
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radix__flush_hugetlb_page(vma, addr);
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set_huge_pte_at(vma->vm_mm, addr, ptep, pte);
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}
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